gem5  [DEVELOP-FOR-23.0]
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
cortex_r52.cc
Go to the documentation of this file.
1 /*
2  * Copyright 2020 Google, Inc.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met: redistributions of source code must retain the above copyright
7  * notice, this list of conditions and the following disclaimer;
8  * redistributions in binary form must reproduce the above copyright
9  * notice, this list of conditions and the following disclaimer in the
10  * documentation and/or other materials provided with the distribution;
11  * neither the name of the copyright holders nor the names of its
12  * contributors may be used to endorse or promote products derived from
13  * this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include "arch/arm/fastmodel/CortexR52/cortex_r52.hh"
29 
30 #include "arch/arm/fastmodel/iris/cpu.hh"
31 #include "base/logging.hh"
32 #include "dev/arm/base_gic.hh"
33 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
34 
35 namespace gem5
36 {
37 
38 namespace fastmodel
39 {
40 
41 void
42 CortexR52::setCluster(CortexR52Cluster *_cluster, int _num)
43 {
44  cluster = _cluster;
45  num = _num;
46 
47  set_evs_param("CFGEND", params().CFGEND);
48  set_evs_param("CFGTE", params().CFGTE);
49  set_evs_param("RVBARADDR", params().RVBARADDR);
50  set_evs_param("ase-present", params().ase_present);
51  set_evs_param("dcache-size", params().dcache_size);
52  set_evs_param("flash.enable", params().flash_enable);
53  set_evs_param("icache-size", params().icache_size);
54  set_evs_param("llpp.base", params().llpp_base);
55  set_evs_param("llpp.size", params().llpp_size);
56  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
57  set_evs_param("min_sync_level", params().min_sync_level);
58  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
59  // Use uint32_t, since the model doesn't like setting these as uint8_t.
60  set_evs_param<uint32_t>("semihosting-ARM_SVC",
61  params().semihosting_ARM_SVC);
62  set_evs_param<uint32_t>("semihosting-T32_HLT",
63  params().semihosting_T32_HLT);
64  set_evs_param<uint32_t>("semihosting-Thumb_SVC",
65  params().semihosting_Thumb_SVC);
66  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
67  set_evs_param("semihosting-cwd", params().semihosting_cwd);
68  set_evs_param("semihosting-enable", params().semihosting_enable);
69  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
70  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
71  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
72  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
73  set_evs_param("tcm.a.enable", params().tcm_a_enable);
74  set_evs_param("tcm.a.size", params().tcm_a_size);
75  set_evs_param("tcm.b.size", params().tcm_b_size);
76  set_evs_param("tcm.c.size", params().tcm_c_size);
77  set_evs_param("vfp-dp-present", params().vfp_dp_present);
78  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
79 }
80 
81 void
82 CortexR52::setResetAddr(Addr addr, bool secure)
83 {
84  evs_base_cpu->setResetAddr(num, addr, secure);
85 }
86 
87 Port &
88 CortexR52::getPort(const std::string &if_name, PortID idx)
89 {
90  if (if_name == "ppi") {
91  // Since PPIs are indexed both by core and by number, modify the name
92  // to hold the core number.
93  return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
94  } else if (if_name == "standbywfi") {
95  // Since standbywfi is indexed by fanout, modify the name to hold the
96  // core number.
97  return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
98  } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash" ||
99  if_name == "core_reset" || if_name == "poweron_reset" ||
100  if_name == "halt") {
101  // Since these ports are scalar per core, use the core number as the
102  // index. Also verify that that index is not being used.
103  assert(idx == InvalidPortID);
104  return evs->gem5_getPort(if_name, num);
105  } else {
106  return SimObject::getPort(if_name, idx);
107  }
108 }
109 
110 CortexR52Cluster::CortexR52Cluster(const Params &p) :
111  SimObject(p), cores(p.cores), evs(p.evs)
112 {
113  for (int i = 0; i < p.cores.size(); i++)
114  p.cores[i]->setCluster(this, i);
115 
116  Iris::BaseCpuEvs *e = dynamic_cast<Iris::BaseCpuEvs *>(evs);
117  panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
118  e->setCluster(this);
119 
120  set_evs_param("core.CLUSTER_ID", params().CLUSTER_ID);
121  set_evs_param("core.DBGROMADDR", params().DBGROMADDR);
122  set_evs_param("core.DBGROMADDRV", params().DBGROMADDRV);
123  set_evs_param("core.PERIPHBASE", params().PERIPHBASE);
124  set_evs_param("core.cluster_utid", params().cluster_utid);
125  set_evs_param("core.cpi_div", params().cpi_div);
126  set_evs_param("core.cpi_mul", params().cpi_mul);
127  set_evs_param("core.dcache-prefetch_enabled",
128  params().dcache_prefetch_enabled);
129  set_evs_param("core.dcache-read_access_latency",
130  params().dcache_read_access_latency);
131  set_evs_param("core.dcache-state_modelled",
132  params().dcache_state_modelled);
133  set_evs_param("core.dcache-write_access_latency",
134  params().dcache_write_access_latency);
135  set_evs_param("core.flash_protection_enable_at_reset",
136  params().flash_protection_enable_at_reset);
137  set_evs_param("core.has_flash_protection", params().has_flash_protection);
138  set_evs_param("core.icache-prefetch_enabled",
139  params().icache_prefetch_enabled);
140  set_evs_param("core.icache-read_access_latency",
141  params().icache_read_access_latency);
142  set_evs_param("core.icache-state_modelled",
143  params().icache_state_modelled);
144  set_evs_param("core.memory.ext_slave_base",
145  params().memory_ext_slave_base);
146  set_evs_param("core.memory.flash_base", params().memory_flash_base);
147  set_evs_param("core.memory.flash_size", params().memory_flash_size);
148  // Use uint32_t, since the model doesn't like setting these as uint8_t.
149  set_evs_param<uint32_t>("core.num_protection_regions_s1",
150  params().num_protection_regions_s1);
151  set_evs_param<uint32_t>("core.num_protection_regions_s2",
152  params().num_protection_regions_s2);
153  set_evs_param("core.num_spi", params().num_spi);
154  set_evs_param("core.ram_protection_enable_at_reset",
155  params().ram_protection_enable_at_reset);
156  set_evs_param("core.has_export_m_port", params().has_export_m_port);
157 }
158 
159 Port &
160 CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
161 {
162  if (if_name == "spi") {
163  return evs->gem5_getPort(if_name, idx);
164  } else if (if_name == "ext_slave" || if_name == "top_reset" ||
165  if_name == "dbg_reset" || if_name == "model_reset") {
166  assert(idx == InvalidPortID);
167  return evs->gem5_getPort(if_name, idx);
168  } else {
169  return SimObject::getPort(if_name, idx);
170  }
171 }
172 
173 } // namespace fastmodel
174 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
gem5::fastmodel::CortexR52Cluster::evs
sc_core::sc_module * evs
Definition: cortex_r52.hh:84
gem5::fastmodel::CortexR52::setResetAddr
void setResetAddr(Addr addr, bool secure=false) override
Definition: cortex_r52.cc:82
gem5::Iris::BaseCpuEvs::setResetAddr
virtual void setResetAddr(int core, Addr addr, bool secure)=0
gem5::fastmodel::CortexR52::setCluster
void setCluster(CortexR52Cluster *_cluster, int _num)
Definition: cortex_r52.cc:42
gem5::fastmodel::CortexR52::cluster
CortexR52Cluster * cluster
Definition: cortex_r52.hh:60
gem5_to_tlm.hh
gem5::fastmodel::CortexR52::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:88
base_gic.hh
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::fastmodel::CortexR52Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:89
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
cpu.hh
gem5::Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:98
gem5::Iris::BaseCPU::evs
sc_core::sc_module * evs
Definition: cpu.hh:96
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::fastmodel::CortexR52::num
int num
Definition: cortex_r52.hh:61
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
cortex_r52.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::fastmodel::CortexR52Cluster
Definition: cortex_r52.hh:80
gem5::fastmodel::CortexR52::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:106
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:214
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
sc_core::sc_module::gem5_getPort
virtual gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
logging.hh
gem5::fastmodel::CortexR52Cluster::CortexR52Cluster
CortexR52Cluster(const Params &p)
Definition: cortex_r52.cc:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::fastmodel::CortexR52Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:160
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
Generated on Sun Jul 30 2023 01:56:47 for gem5 by doxygen 1.8.17