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cpu.hh
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37 
44 #ifndef __CPU_MINOR_CPU_HH__
45 #define __CPU_MINOR_CPU_HH__
46 
47 #include "base/compiler.hh"
48 #include "base/random.hh"
49 #include "cpu/base.hh"
50 #include "cpu/minor/activity.hh"
51 #include "cpu/minor/stats.hh"
52 #include "cpu/simple_thread.hh"
53 #include "enums/ThreadPolicy.hh"
54 #include "params/BaseMinorCPU.hh"
55 
56 namespace gem5
57 {
58 
59 namespace minor
60 {
61 
64 class Pipeline;
65 
68 
69 } // namespace minor
70 
84 class MinorCPU : public BaseCPU
85 {
86  protected:
90 
91  public:
96 
101 
102  public:
105  class MinorCPUPort : public RequestPort
106  {
107  public:
110 
111  public:
112  MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
113  : RequestPort(name_), cpu(cpu_)
114  { }
115 
116  };
117 
119  enums::ThreadPolicy threadPolicy;
120  protected:
122  Port &getDataPort() override;
123 
125  Port &getInstPort() override;
126 
127  public:
128  MinorCPU(const BaseMinorCPUParams &params);
129 
130  ~MinorCPU();
131 
132  public:
134  void init() override;
135  void startup() override;
136  void wakeup(ThreadID tid) override;
137 
140 
142  void regStats() override;
143 
145  Counter totalInsts() const override;
146  Counter totalOps() const override;
147 
148  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
149  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
150 
152  void serialize(CheckpointOut &cp) const override;
153  void unserialize(CheckpointIn &cp) override;
154 
156  DrainState drain() override;
157  void drainResume() override;
160  void signalDrainDone();
161  void memWriteback() override;
162 
164  void switchOut() override;
165  void takeOverFrom(BaseCPU *old_cpu) override;
166 
168  void activateContext(ThreadID thread_id) override;
169  void suspendContext(ThreadID thread_id) override;
170 
173  {
174  std::vector<ThreadID> prio_list;
175  for (ThreadID i = 1; i <= numThreads; i++) {
176  prio_list.push_back((priority + i) % numThreads);
177  }
178  return prio_list;
179  }
180 
182  {
183  std::vector<ThreadID> prio_list;
184  for (ThreadID i = 0; i < numThreads; i++) {
185  prio_list.push_back(i);
186  }
187 
188  std::shuffle(prio_list.begin(), prio_list.end(),
189  random_mt.gen);
190 
191  return prio_list;
192  }
193 
199 
204  void wakeupOnEvent(unsigned int stage_id);
206 };
207 
208 } // namespace gem5
209 
210 #endif /* __CPU_MINOR_CPU_HH__ */
gem5::MinorCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu.cc:244
gem5::MinorCPU::randomPriority
std::vector< ThreadID > randomPriority()
Definition: cpu.hh:181
gem5::MinorCPU::pipeline
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:89
gem5::MinorCPU::MinorCPUPort::MinorCPUPort
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:112
gem5::MinorCPU::memWriteback
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition: cpu.cc:226
gem5::minor::MinorActivityRecorder
ActivityRecorder with a Ticked interface.
Definition: activity.hh:57
gem5::MinorCPU::tick
void tick()
The tick method in the MinorCPU is simply updating the cycle counters as the ticking of the pipeline ...
Definition: cpu.hh:198
gem5::MinorCPU::MinorCPUPort
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:105
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:561
random.hh
gem5::MinorCPU::MinorCPUPort::cpu
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:109
minor
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:84
std::vector
STL vector class.
Definition: stl.hh:37
gem5::MinorCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: cpu.cc:196
gem5::MinorCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:136
stats.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::Random::gen
std::mt19937_64 gen
Definition: random.hh:69
gem5::MinorCPU::totalInsts
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:313
gem5::MinorCPU::wakeupOnEvent
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:291
gem5::MinorCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:307
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:100
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:118
gem5::MinorCPU::stats
minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:139
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:384
gem5::ArmISA::priority
Bitfield< 3, 0 > priority
Definition: misc_types.hh:833
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::MinorCPU::MinorCPU
MinorCPU(const BaseMinorCPUParams &params)
Definition: cpu.cc:50
gem5::MinorCPU::regStats
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:110
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::MinorCPU::totalOps
Counter totalOps() const override
Definition: cpu.cc:324
gem5::BaseCPU::CPU_STATE_ON
@ CPU_STATE_ON
Definition: base.hh:551
gem5::MinorCPU::init
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:98
gem5::BaseCPU
Definition: base.hh:104
gem5::MinorCPU::suspendContext
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition: cpu.cc:281
gem5::MinorCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:129
compiler.hh
gem5::minor::Pipeline
The constructed pipeline.
Definition: pipeline.hh:72
gem5::MinorCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.cc:143
gem5::MinorCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:123
gem5::MinorCPU::~MinorCPU
~MinorCPU()
Definition: cpu.cc:85
gem5::MinorCPU::signalDrainDone
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition: cpu.cc:189
gem5::MinorCPU::drain
DrainState drain() override
Drain interface.
Definition: cpu.cc:165
gem5::MinorCPU::activateContext
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:252
gem5::EventFunctionWrapper
Definition: eventq.hh:1136
simple_thread.hh
gem5::MinorCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:117
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::minor::MinorThread
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:64
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:46
gem5::MinorCPU::switchOut
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:232
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MinorCPU::threadPolicy
enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition: cpu.hh:119
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:95
gem5::MinorCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:301
gem5::minor::MinorStats
Currently unused stats class.
Definition: stats.hh:58
gem5::MinorCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:154
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::random_mt
Random random_mt
Definition: random.cc:99
activity.hh
gem5::MinorCPU::fetchEventWrapper
EventFunctionWrapper * fetchEventWrapper
Definition: cpu.hh:205
gem5::MinorCPU::roundRobinPriority
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition: cpu.hh:172
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235

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