fetch2.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __CPU_MINOR_FETCH2_HH__
#define __CPU_MINOR_FETCH2_HH__
 
#include <vector>
 
#include "base/named.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/pred/bpred_unit.hh"
#include "params/BaseMinorCPU.hh"
 
namespace gem5
{
 
namespace minor
{
 
class Fetch2 : public Named
{
  protected:
    MinorCPU &cpu;
 
    Latch<ForwardLineData>::Output inp;
 
    Latch<BranchData>::Output branchInp;
 
    Latch<BranchData>::Input predictionOut;
 
    Latch<ForwardInstData>::Input out;
 
    std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;
 
    unsigned int outputWidth;
 
    bool processMoreThanOneInput;
 
    branch_prediction::BPredUnit &branchPredictor;
 
  public:
    /* Public so that Pipeline can pass it to Fetch1 */
    std::vector<InputBuffer<ForwardLineData>> inputBuffer;
 
  protected:
    struct Fetch2ThreadInfo
    {
        Fetch2ThreadInfo() {}
 
        Fetch2ThreadInfo(const Fetch2ThreadInfo& other) :
            inputIndex(other.inputIndex),
            havePC(other.havePC),
            lastStreamSeqNum(other.lastStreamSeqNum),
            expectedStreamSeqNum(other.expectedStreamSeqNum),
            predictionSeqNum(other.predictionSeqNum),
            blocked(other.blocked)
        {
            set(pc, other.pc);
        }
 
        unsigned int inputIndex = 0;
 
 
        std::unique_ptr<PCStateBase> pc;
 
        bool havePC = false;
 
        InstSeqNum lastStreamSeqNum = InstId::firstStreamSeqNum;
 
        InstSeqNum fetchSeqNum = InstId::firstFetchSeqNum;
 
        InstSeqNum expectedStreamSeqNum = InstId::firstStreamSeqNum;
 
        InstSeqNum predictionSeqNum = InstId::firstPredictionSeqNum;
 
        bool blocked = false;
    };
 
    std::vector<Fetch2ThreadInfo> fetchInfo;
    ThreadID threadPriority;
 
    struct Fetch2Stats : public statistics::Group
    {
        Fetch2Stats(MinorCPU *cpu);
        statistics::Scalar intInstructions;
        statistics::Scalar fpInstructions;
        statistics::Scalar vecInstructions;
        statistics::Scalar loadInstructions;
        statistics::Scalar storeInstructions;
        statistics::Scalar amoInstructions;
    } stats;
 
  protected:
    const ForwardLineData *getInput(ThreadID tid);
 
    void popInput(ThreadID tid);
 
    void dumpAllInput(ThreadID tid);
 
    void updateBranchPrediction(const BranchData &branch);
 
    void predictBranch(MinorDynInstPtr inst, BranchData &branch);
 
    ThreadID getScheduledThread();
 
  public:
    Fetch2(const std::string &name,
        MinorCPU &cpu_,
        const BaseMinorCPUParams &params,
        Latch<ForwardLineData>::Output inp_,
        Latch<BranchData>::Output branchInp_,
        Latch<BranchData>::Input predictionOut_,
        Latch<ForwardInstData>::Input out_,
        std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
 
  public:
    void evaluate();
 
    void minorTrace() const;
 
 
    bool isDrained();
};
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_FETCH2_HH__ */