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mat.hh
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37 
38 #ifndef __ARCH_ARM_REGS_MAT_HH__
39 #define __ARCH_ARM_REGS_MAT_HH__
40 
41 #include "arch/arm/types.hh"
42 #include "arch/arm/matrix.hh"
43 #include "cpu/reg_class.hh"
44 #include "debug/MatRegs.hh"
45 
46 namespace gem5
47 {
48 
49 namespace ArmISA
50 {
51 
52 /*
53  * We do the same as is done for vector registers when creating the
54  * matricies. One of the things to note is that this allocates the
55  * largest architecturally possible matrix - this is a bit inefficient
56  * from a memory point of view, but at this point we do not know which
57  * vector length will be chosen (and this can potentially vary during
58  * runtime).
59  */
62 
63 template<typename ElemType>
64 using MatTile = gem5::Tile<ElemType,
66 
67 template<typename ElemType>
68 using MatTileRow = gem5::HorizontalSlice<ElemType,
70  true>;
71 
72 template<typename ElemType>
73 using MatTileCol = gem5::VerticalSlice<ElemType,
75  true>;
76 
77 template<typename ElemType>
78 using MatRow = gem5::HorizontalSlice<ElemType,
80  false>;
81 
82 template<typename ElemType>
83 using MatCol = gem5::VerticalSlice<ElemType,
85  false>;
86 
87 // SME ZA tile, i.e. matrix
88 const int NumMatrixRegs = 1;
89 
91 
92 inline constexpr RegClass matRegClass =
94  ops(matRegClassOps).
95  regType<MatRegContainer>();
96 
97 /*
98  * Helpers for providing access to the different views of a matrix
99  * register. Intended to be called from the instruction implementations
100  * themselves.
101  */
102 template<typename ElemType>
104 getTile(MatRegContainer &reg, uint8_t tile_idx)
105 {
106  return reg.asTile<ElemType>(tile_idx);
107 }
108 template<typename ElemType>
110 getTileHSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
111 {
112  return reg.asTile<ElemType>(tile_idx).asHSlice(row_idx);
113 }
114 template<typename ElemType>
116 getTileVSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
117 {
118  return reg.asTile<ElemType>(tile_idx).asVSlice(col_idx);
119 }
120 template<typename ElemType>
122 getHSlice(MatRegContainer &reg, uint8_t row_idx)
123 {
124  return reg.asHSlice<ElemType>(row_idx);
125 }
126 template<typename ElemType>
128 getVSlice(MatRegContainer &reg, uint8_t col_idx)
129 {
130  return reg.asVSlice<ElemType>(col_idx);
131 }
132 
133 } // namespace ArmISA
134 } // namespace gem5
135 
136 #endif
gem5::Tile
Provides a view of a matrix that is row-interleaved onto a MatStore.
Definition: matrix.hh:131
gem5::MatStore
Backing store for matrices.
Definition: matrix.hh:129
gem5::ArmISA::getVSlice
MatCol< ElemType > getVSlice(MatRegContainer &reg, uint8_t col_idx)
Definition: mat.hh:128
gem5::ArmISA::getTile
MatTile< ElemType > getTile(MatRegContainer &reg, uint8_t tile_idx)
Definition: mat.hh:104
gem5::ArmISA::getHSlice
MatRow< ElemType > getHSlice(MatRegContainer &reg, uint8_t row_idx)
Definition: mat.hh:122
gem5::ArmISA::NumMatrixRegs
const int NumMatrixRegs
Definition: mat.hh:88
gem5::TypedRegClassOps
Definition: reg_class.hh:358
types.hh
matrix.hh
gem5::ArmISA::matRegClassOps
static TypedRegClassOps< ArmISA::MatRegContainer > matRegClassOps
Definition: mat.hh:90
gem5::MatRegClass
@ MatRegClass
Matrix Register.
Definition: reg_class.hh:67
gem5::ArmISA::MaxSmeVecLenInBytes
constexpr unsigned MaxSmeVecLenInBytes
Definition: types.hh:484
gem5::HorizontalSlice
Provides a view of a horizontal slice of either a MatStore or a Tile.
Definition: matrix.hh:151
gem5::MatRegClassName
constexpr char MatRegClassName[]
Definition: reg_class.hh:79
gem5::RegClass
Definition: reg_class.hh:184
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::VerticalSlice
Provides a view of a vertical slice of either a MatStore or a Tile.
Definition: matrix.hh:224
gem5::ArmISA::MatRegContainer
gem5::MatStore< MaxSmeVecLenInBytes, MaxSmeVecLenInBytes > MatRegContainer
Definition: mat.hh:61
reg_class.hh
gem5::ArmISA::getTileHSlice
MatTileRow< ElemType > getTileHSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
Definition: mat.hh:110
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::matRegClass
constexpr RegClass matRegClass
Definition: mat.hh:92
gem5::ArmISA::getTileVSlice
MatTileCol< ElemType > getTileVSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
Definition: mat.hh:116

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