decode.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __CPU_MINOR_DECODE_HH__
#define __CPU_MINOR_DECODE_HH__
 
#include <vector>
 
#include "base/named.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/dyn_inst.hh"
#include "cpu/minor/pipe_data.hh"
 
namespace gem5
{
 
namespace minor
{
 
/* Decode takes instructions from Fetch2 and decomposes them into micro-ops
 * to feed to Execute.  It generates a new sequence number for each
 * instruction: execSeqNum.
 */
class Decode : public Named
{
  protected:
    MinorCPU &cpu;
 
    Latch<ForwardInstData>::Output inp;
    Latch<ForwardInstData>::Input out;
 
    std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;
 
    unsigned int outputWidth;
 
    bool processMoreThanOneInput;
 
  public:
    /* Public for Pipeline to be able to pass it to Fetch2 */
    std::vector<InputBuffer<ForwardInstData>> inputBuffer;
 
  protected:
    struct DecodeThreadInfo
    {
        DecodeThreadInfo() {}
 
        DecodeThreadInfo(const DecodeThreadInfo& other) :
            inputIndex(other.inputIndex),
            inMacroop(other.inMacroop),
            execSeqNum(other.execSeqNum),
            blocked(other.blocked)
        {
            set(microopPC, other.microopPC);
        }
 
 
        unsigned int inputIndex = 0;
 
        bool inMacroop = false;
        std::unique_ptr<PCStateBase> microopPC;
 
        InstSeqNum execSeqNum = InstId::firstExecSeqNum;
 
        bool blocked = false;
    };
 
    std::vector<DecodeThreadInfo> decodeInfo;
    ThreadID threadPriority;
 
  protected:
    const ForwardInstData *getInput(ThreadID tid);
 
    void popInput(ThreadID tid);
 
    ThreadID getScheduledThread();
  public:
    Decode(const std::string &name,
        MinorCPU &cpu_,
        const BaseMinorCPUParams &params,
        Latch<ForwardInstData>::Output inp_,
        Latch<ForwardInstData>::Input out_,
        std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
 
  public:
    void evaluate();
 
    void minorTrace() const;
 
    bool isDrained();
};
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_DECODE_HH__ */