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pmp.hh
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29 
30 #ifndef __ARCH_RISCV_PMP_HH__
31 #define __ARCH_RISCV_PMP_HH__
32 
33 #include "arch/generic/tlb.hh"
34 #include "arch/riscv/isa.hh"
35 #include "base/addr_range.hh"
36 #include "base/types.hh"
37 #include "mem/packet.hh"
38 #include "params/PMP.hh"
39 #include "sim/sim_object.hh"
40 
46 namespace gem5
47 {
48 
54 class PMP : public SimObject
55 {
56  public:
57  PARAMS(PMP);
58  PMP(const Params &params);
59 
60  private:
63 
72  enum pmpAmatch
73  {
78  };
79 
81  const uint8_t PMP_READ = 1 << 0;
82 
84  const uint8_t PMP_WRITE = 1 << 1;
85 
87  const uint8_t PMP_EXEC = 1 << 2;
88 
90  const uint8_t PMP_A_MASK = 3 << 3;
91 
93  const uint8_t PMP_LOCK = 1 << 7;
94 
96  int numRules;
97 
100 
102  struct PmpEntry
103  {
109  uint8_t pmpCfg = 0;
110  };
111 
114 
115  public:
129  Addr vaddr = 0);
130 
139  bool pmpUpdateCfg(uint32_t pmp_index, uint8_t this_cfg);
140 
149  bool pmpUpdateAddr(uint32_t pmp_index, Addr this_addr);
150 
155  void pmpReset();
156 
157  private:
167 
179 
186  void pmpUpdateRule(uint32_t pmp_index);
187 
194  inline uint8_t pmpGetAField(uint8_t cfg);
195 
204  inline AddrRange pmpDecodeNapot(Addr pmpaddr);
205 
206 };
207 
208 } // namespace gem5
209 
210 #endif // __ARCH_RISCV_PMP_HH__
gem5::PMP
This class helps to implement RISCV's physical memory protection (pmp) primitive.
Definition: pmp.hh:54
gem5::PMP::PmpEntry::pmpCfg
uint8_t pmpCfg
pmpcfg reg value for a pmp entry
Definition: pmp.hh:109
gem5::PMP::PMP_OFF
@ PMP_OFF
Definition: pmp.hh:74
gem5::PMP::PMP
PMP(const Params &params)
Definition: pmp.cc:47
gem5::PMP::PmpEntry
single pmp entry struct
Definition: pmp.hh:102
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
tlb.hh
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:55
gem5::PMP::shouldCheckPMP
bool shouldCheckPMP(RiscvISA::PrivilegeMode pmode, ThreadContext *tc)
This function is called during a memory access to determine if the pmp table should be consulted for ...
Definition: pmp.cc:273
gem5::PMP::hasLockEntry
bool hasLockEntry
variable to keep track of any lock of entry
Definition: pmp.hh:99
std::vector
STL vector class.
Definition: stl.hh:37
gem5::PMP::pmpUpdateRule
void pmpUpdateRule(uint32_t pmp_index)
pmpUpdateRule updates the pmp rule for a given pmp entry depending on the value of pmpaddr and pmpcfg...
Definition: pmp.cc:172
gem5::PMP::pmpAmatch
pmpAmatch
This enum is used for encoding of address matching mode of pmp address register, which is present in ...
Definition: pmp.hh:72
gem5::PMP::PMP_NAPOT
@ PMP_NAPOT
Definition: pmp.hh:77
isa.hh
gem5::PMP::pmpUpdateAddr
bool pmpUpdateAddr(uint32_t pmp_index, Addr this_addr)
pmpUpdateAddr updates the pmpaddr for a pmp entry and calls pmpUpdateRule to update the rule of corre...
Definition: pmp.cc:236
packet.hh
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::PMP::numRules
int numRules
variable to keep track of active number of rules any time
Definition: pmp.hh:96
gem5::PMP::PmpEntry::rawAddr
Addr rawAddr
raw addr in pmpaddr register for a pmp entry
Definition: pmp.hh:107
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::PMP::pmpCheck
Fault pmpCheck(const RequestPtr &req, BaseMMU::Mode mode, RiscvISA::PrivilegeMode pmode, ThreadContext *tc, Addr vaddr=0)
pmpCheck checks if a particular memory access is allowed based on the pmp rules.
Definition: pmp.cc:57
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::PMP::PMP_NA4
@ PMP_NA4
Definition: pmp.hh:76
gem5::PMP::pmpReset
void pmpReset()
pmpReset reset when reset signal in trigger from CPU.
Definition: pmp.cc:227
gem5::PMP::PmpEntry::pmpAddr
AddrRange pmpAddr
addr range corresponding to a single pmp entry
Definition: pmp.hh:105
gem5::PMP::createAddrfault
Fault createAddrfault(Addr vaddr, BaseMMU::Mode mode)
createAddrfault creates an address fault if the pmp checks fail to pass for a given access.
Definition: pmp.cc:126
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PMP::PMP_EXEC
const uint8_t PMP_EXEC
pmpcfg address range execute permission mask
Definition: pmp.hh:87
addr_range.hh
gem5::PMP::pmpUpdateCfg
bool pmpUpdateCfg(uint32_t pmp_index, uint8_t this_cfg)
pmpUpdateCfg updates the pmpcfg for a pmp entry and calls pmpUpdateRule to update the rule of corresp...
Definition: pmp.cc:150
gem5::PMP::PMP_WRITE
const uint8_t PMP_WRITE
pmpcfg address range write permission mask
Definition: pmp.hh:84
gem5::PMP::pmpDecodeNapot
AddrRange pmpDecodeNapot(Addr pmpaddr)
This function decodes a pmpaddr register value into an address range when A field of pmpcfg register ...
Definition: pmp.cc:284
gem5::PMP::pmpGetAField
uint8_t pmpGetAField(uint8_t cfg)
pmpGetAField extracts the A field (address matching mode) from an input pmpcfg register
Definition: pmp.cc:141
gem5::PMP::PMP_LOCK
const uint8_t PMP_LOCK
pmpcfg address range locked mask
Definition: pmp.hh:93
gem5::PMP::PMP_TOR
@ PMP_TOR
Definition: pmp.hh:75
types.hh
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::PMP::PARAMS
PARAMS(PMP)
gem5::PMP::PMP_READ
const uint8_t PMP_READ
pmpcfg address range read permission mask
Definition: pmp.hh:81
gem5::PMP::pmpEntries
int pmpEntries
maximum number of entries in the pmp table
Definition: pmp.hh:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PMP::PMP_A_MASK
const uint8_t PMP_A_MASK
pmpcfg A field mask
Definition: pmp.hh:90
gem5::PMP::pmpTable
std::vector< PmpEntry > pmpTable
a table of pmp entries
Definition: pmp.hh:113
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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