gem5  v21.1.0.2
gpu_static_inst.hh
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33 
34 #ifndef __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
35 #define __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
36 
42 #include "gpu-compute/wavefront.hh"
43 
44 namespace gem5
45 {
46 
47 namespace VegaISA
48 {
50  {
51  public:
52  VEGAGPUStaticInst(const std::string &opcode);
54 
55  void generateDisassembly() override { disassembly = _opcode; }
56 
57  bool
58  isFlatScratchRegister(int opIdx) override
59  {
60  return isFlatScratchReg(opIdx);
61  }
62 
63  void initOperandInfo() override { return; }
64  int getOperandSize(int opIdx) override { return 0; }
65 
73  int coalescerTokenCount() const override { return 1; }
74  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
75 
76  protected:
77  void panicUnimplemented() const;
78 
85  }; // class VEGAGPUStaticInst
86 
87 } // namespace VegaISA
88 } // namespace gem5
89 
90 #endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
operand.hh
gem5::VegaISA::VEGAGPUStaticInst
Definition: gpu_static_inst.hh:49
gem5::VegaISA::VEGAGPUStaticInst::~VEGAGPUStaticInst
~VEGAGPUStaticInst()
Definition: gpu_static_inst.cc:52
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:300
gem5::VegaISA::VEGAGPUStaticInst::_srcLiteral
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
Definition: gpu_static_inst.hh:84
gpu_static_inst.hh
gem5::VegaISA::VEGAGPUStaticInst::panicUnimplemented
void panicUnimplemented() const
Definition: gpu_static_inst.cc:57
gem5::VegaISA::VEGAGPUStaticInst::getOperandSize
int getOperandSize(int opIdx) override
Definition: gpu_static_inst.hh:64
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
wavefront.hh
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:264
vector_register_file.hh
gem5::VegaISA::VEGAGPUStaticInst::VEGAGPUStaticInst
VEGAGPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:47
gem5::VegaISA::VEGAGPUStaticInst::srcLiteral
ScalarRegU32 srcLiteral() const override
Definition: gpu_static_inst.hh:74
scalar_register_file.hh
gpu_registers.hh
gem5::VegaISA::VEGAGPUStaticInst::generateDisassembly
void generateDisassembly() override
Definition: gpu_static_inst.hh:55
gem5::VegaISA::VEGAGPUStaticInst::initOperandInfo
void initOperandInfo() override
Definition: gpu_static_inst.hh:63
gem5::GPUStaticInst::_opcode
const std::string _opcode
Definition: gpu_static_inst.hh:299
gem5::VegaISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:221
gem5::VegaISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VegaISA::VEGAGPUStaticInst::isFlatScratchRegister
bool isFlatScratchRegister(int opIdx) override
Definition: gpu_static_inst.hh:58
gem5::VegaISA::VEGAGPUStaticInst::coalescerTokenCount
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
Definition: gpu_static_inst.hh:73

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