gem5 v24.0.0.0
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gpu_static_inst.hh
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1/*
2 * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
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18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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30 */
31
32#ifndef __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
33#define __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
34
41
42namespace gem5
43{
44
45namespace VegaISA
46{
48 {
49 public:
50 VEGAGPUStaticInst(const std::string &opcode);
52
54
55 bool
56 isFlatScratchRegister(int opIdx) override
57 {
58 return isFlatScratchReg(opIdx);
59 }
60
61 bool
62 isExecMaskRegister(int opIdx) override
63 {
64 return isExecMask(opIdx);
65 }
66
67 void initOperandInfo() override { return; }
68 int getOperandSize(int opIdx) override { return 0; }
69
77 int coalescerTokenCount() const override { return 1; }
78 ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
79
80 protected:
81 void panicUnimplemented() const;
82
89 }; // class VEGAGPUStaticInst
90
91} // namespace VegaISA
92} // namespace gem5
93
94#endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
const std::string & opcode() const
const std::string _opcode
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
bool isFlatScratchRegister(int opIdx) override
ScalarRegU32 srcLiteral() const override
int getOperandSize(int opIdx) override
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
bool isExecMaskRegister(int opIdx) override
VEGAGPUStaticInst(const std::string &opcode)
bool isFlatScratchReg(int opIdx)
bool isExecMask(int opIdx)
uint32_t ScalarRegU32
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

Generated on Tue Jun 18 2024 16:24:04 for gem5 by doxygen 1.11.0