gem5  v22.1.0.0
gpu_static_inst.hh
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31 
32 #ifndef __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
33 #define __ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
34 
40 #include "gpu-compute/wavefront.hh"
41 
42 namespace gem5
43 {
44 
45 namespace VegaISA
46 {
48  {
49  public:
50  VEGAGPUStaticInst(const std::string &opcode);
52 
53  void generateDisassembly() override { disassembly = _opcode; }
54 
55  bool
56  isFlatScratchRegister(int opIdx) override
57  {
58  return isFlatScratchReg(opIdx);
59  }
60 
61  bool
62  isExecMaskRegister(int opIdx) override
63  {
64  return isExecMask(opIdx);
65  }
66 
67  void initOperandInfo() override { return; }
68  int getOperandSize(int opIdx) override { return 0; }
69 
77  int coalescerTokenCount() const override { return 1; }
78  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
79 
80  protected:
81  void panicUnimplemented() const;
82 
89  }; // class VEGAGPUStaticInst
90 
91 } // namespace VegaISA
92 } // namespace gem5
93 
94 #endif //__ARCH_VEGA_INSTS_GPU_STATIC_INST_HH__
const std::string & opcode() const
const std::string _opcode
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
bool isFlatScratchRegister(int opIdx) override
ScalarRegU32 srcLiteral() const override
int getOperandSize(int opIdx) override
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
bool isExecMaskRegister(int opIdx) override
VEGAGPUStaticInst(const std::string &opcode)
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:222
bool isExecMask(int opIdx)
Definition: registers.cc:210
uint32_t ScalarRegU32
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

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