gem5  v21.1.0.2
gpu_static_inst.hh
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33 
34 #ifndef __GPU_STATIC_INST_HH__
35 #define __GPU_STATIC_INST_HH__
36 
37 /*
38  * @file gpu_static_inst.hh
39  *
40  * Defines the base class representing static instructions for the GPU. The
41  * instructions are "static" because they contain no dynamic instruction
42  * information. GPUStaticInst corresponds to the StaticInst class for the CPU
43  * models.
44  */
45 
46 #include <cstdint>
47 #include <string>
48 #include <vector>
49 
50 #include "enums/GPUStaticInstFlags.hh"
51 #include "enums/StorageClassType.hh"
53 #include "gpu-compute/misc.hh"
55 #include "gpu-compute/wavefront.hh"
56 
57 namespace gem5
58 {
59 
60 class BaseOperand;
61 class BaseRegOperand;
62 
63 class GPUStaticInst : public GPUStaticInstFlags
64 {
65  public:
66  GPUStaticInst(const std::string &opcode);
67  virtual ~GPUStaticInst() { }
68  void instAddr(int inst_addr) { _instAddr = inst_addr; }
69  int instAddr() const { return _instAddr; }
70  int nextInstAddr() const { return _instAddr + instSize(); }
71 
72  void instNum(int num) { _instNum = num; }
73 
74  int instNum() { return _instNum; }
75 
76  void ipdInstNum(int num) { _ipdInstNum = num; }
77 
78  int ipdInstNum() const { return _ipdInstNum; }
79 
80  virtual TheGpuISA::ScalarRegU32 srcLiteral() const { return 0; }
81 
83 
84  virtual void initOperandInfo() = 0;
85  virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
86  virtual void generateDisassembly() = 0;
87  const std::string& disassemble();
88  virtual int getNumOperands() = 0;
89  virtual bool isFlatScratchRegister(int opIdx) = 0;
90  virtual bool isExecMaskRegister(int opIdx) = 0;
91  virtual int getOperandSize(int operandIndex) = 0;
92 
93  virtual int numDstRegOperands() = 0;
94  virtual int numSrcRegOperands() = 0;
95 
96  int numSrcVecOperands();
97  int numDstVecOperands();
98  int numSrcVecDWords();
99  int numDstVecDWords();
100 
101  int numSrcScalarOperands();
102  int numDstScalarOperands();
103  int numSrcScalarDWords();
104  int numDstScalarDWords();
105 
106  int maxOperandSize();
107 
108  virtual int coalescerTokenCount() const { return 0; }
109 
110  bool isALU() const { return _flags[ALU]; }
111  bool isBranch() const { return _flags[Branch]; }
112  bool isCondBranch() const { return _flags[CondBranch]; }
113  bool isNop() const { return _flags[Nop]; }
114  bool isReturn() const { return _flags[Return]; }
115  bool isEndOfKernel() const { return _flags[EndOfKernel]; }
116  bool isKernelLaunch() const { return _flags[KernelLaunch]; }
117  bool isSDWAInst() const { return _flags[IsSDWA]; }
118  bool isDPPInst() const { return _flags[IsDPP]; }
119 
120  bool
122  {
123  return _flags[UnconditionalJump];
124  }
125 
126  bool isSpecialOp() const { return _flags[SpecialOp]; }
127  bool isWaitcnt() const { return _flags[Waitcnt]; }
128  bool isSleep() const { return _flags[Sleep]; }
129 
130  bool isBarrier() const { return _flags[MemBarrier]; }
131  bool isMemSync() const { return _flags[MemSync]; }
132  bool isMemRef() const { return _flags[MemoryRef]; }
133  bool isFlat() const { return _flags[Flat]; }
134  bool isLoad() const { return _flags[Load]; }
135  bool isStore() const { return _flags[Store]; }
136 
137  bool
138  isAtomic() const
139  {
140  return _flags[AtomicReturn] || _flags[AtomicNoReturn];
141  }
142 
143  bool isAtomicNoRet() const { return _flags[AtomicNoReturn]; }
144  bool isAtomicRet() const { return _flags[AtomicReturn]; }
145 
146  bool isScalar() const { return _flags[Scalar]; }
147  bool readsSCC() const { return _flags[ReadsSCC]; }
148  bool writesSCC() const { return _flags[WritesSCC]; }
149  bool readsVCC() const { return _flags[ReadsVCC]; }
150  bool writesVCC() const { return _flags[WritesVCC]; }
151  // Identify instructions that implicitly read the Execute mask
152  // as a source operand but not to dictate which threads execute.
153  bool readsEXEC() const { return _flags[ReadsEXEC]; }
154  bool writesEXEC() const { return _flags[WritesEXEC]; }
155  bool readsMode() const { return _flags[ReadsMode]; }
156  bool writesMode() const { return _flags[WritesMode]; }
157  bool ignoreExec() const { return _flags[IgnoreExec]; }
158 
159  bool isAtomicAnd() const { return _flags[AtomicAnd]; }
160  bool isAtomicOr() const { return _flags[AtomicOr]; }
161  bool isAtomicXor() const { return _flags[AtomicXor]; }
162  bool isAtomicCAS() const { return _flags[AtomicCAS]; }
163  bool isAtomicExch() const { return _flags[AtomicExch]; }
164  bool isAtomicAdd() const { return _flags[AtomicAdd]; }
165  bool isAtomicSub() const { return _flags[AtomicSub]; }
166  bool isAtomicInc() const { return _flags[AtomicInc]; }
167  bool isAtomicDec() const { return _flags[AtomicDec]; }
168  bool isAtomicMax() const { return _flags[AtomicMax]; }
169  bool isAtomicMin() const { return _flags[AtomicMin]; }
170 
171  bool
172  isArgLoad() const
173  {
174  return (_flags[KernArgSegment] || _flags[ArgSegment]) && _flags[Load];
175  }
176 
177  bool
178  isGlobalMem() const
179  {
180  return _flags[MemoryRef] && (_flags[GlobalSegment] ||
181  _flags[PrivateSegment] || _flags[ReadOnlySegment] ||
182  _flags[SpillSegment]);
183  }
184 
185  bool
186  isLocalMem() const
187  {
188  return _flags[MemoryRef] && _flags[GroupSegment];
189  }
190 
191  bool isArgSeg() const { return _flags[ArgSegment]; }
192  bool isGlobalSeg() const { return _flags[GlobalSegment]; }
193  bool isGroupSeg() const { return _flags[GroupSegment]; }
194  bool isKernArgSeg() const { return _flags[KernArgSegment]; }
195  bool isPrivateSeg() const { return _flags[PrivateSegment]; }
196  bool isReadOnlySeg() const { return _flags[ReadOnlySegment]; }
197  bool isSpillSeg() const { return _flags[SpillSegment]; }
198 
209  bool isGloballyCoherent() const { return _flags[GloballyCoherent]; }
210  bool isSystemCoherent() const { return _flags[SystemCoherent]; }
211 
212  // Floating-point instructions
213  bool isF16() const { return _flags[F16]; }
214  bool isF32() const { return _flags[F32]; }
215  bool isF64() const { return _flags[F64]; }
216 
217  // FMA, MAC, MAD instructions
218  bool isFMA() const { return _flags[FMA]; }
219  bool isMAC() const { return _flags[MAC]; }
220  bool isMAD() const { return _flags[MAD]; }
221 
222  virtual int instSize() const = 0;
223 
224  // only used for memory instructions
225  virtual void
227  {
228  fatal("calling initiateAcc() on a non-memory instruction.\n");
229  }
230 
231  // only used for memory instructions
232  virtual void
234  {
235  fatal("calling completeAcc() on a non-memory instruction.\n");
236  }
237 
238  virtual uint32_t getTargetPc() { return 0; }
239 
240  static uint64_t dynamic_id_count;
241 
242  // For flat memory accesses
243  enums::StorageClassType executed_as;
244 
245  void setFlag(Flags flag) {
246  _flags[flag] = true;
247 
248  if (isGroupSeg()) {
249  executed_as = enums::SC_GROUP;
250  } else if (isGlobalSeg()) {
251  executed_as = enums::SC_GLOBAL;
252  } else if (isPrivateSeg()) {
253  executed_as = enums::SC_PRIVATE;
254  } else if (isSpillSeg()) {
255  executed_as = enums::SC_SPILL;
256  } else if (isReadOnlySeg()) {
257  executed_as = enums::SC_READONLY;
258  } else if (isKernArgSeg()) {
259  executed_as = enums::SC_KERNARG;
260  } else if (isArgSeg()) {
261  executed_as = enums::SC_ARG;
262  }
263  }
264  const std::string& opcode() const { return _opcode; }
265 
266  const std::vector<OperandInfo>& srcOperands() const { return srcOps; }
267  const std::vector<OperandInfo>& dstOperands() const { return dstOps; }
268 
271  {
272  return srcVecRegOps;
273  }
274 
277  {
278  return dstVecRegOps;
279  }
280 
283  {
284  return srcScalarRegOps;
285  }
286 
289  {
290  return dstScalarRegOps;
291  }
292 
293  // These next 2 lines are used in initDynOperandInfo to let the lambda
294  // function work
295  typedef int (RegisterManager::*MapRegFn)(Wavefront *, int);
297 
298  protected:
299  const std::string _opcode;
300  std::string disassembly;
301  int _instNum;
305 
306  private:
312 
317 
322 
323  std::bitset<Num_Flags> _flags;
324 };
325 
327 {
328  public:
330  {
331  setFlag(Nop);
332  setFlag(KernelLaunch);
333  setFlag(MemSync);
334  setFlag(Scalar);
335  setFlag(GlobalSegment);
336  }
337 
338  void
339  execute(GPUDynInstPtr gpuDynInst) override
340  {
341  fatal("kernel launch instruction should not be executed\n");
342  }
343 
344  void
346  {
348  }
349 
350  void initOperandInfo() override { return; }
351  int getNumOperands() override { return 0; }
352  bool isFlatScratchRegister(int opIdx) override { return false; }
353  // return true if the Execute mask is explicitly used as a source
354  // register operand
355  bool isExecMaskRegister(int opIdx) override { return false; }
356  int getOperandSize(int operandIndex) override { return 0; }
357 
358  int numDstRegOperands() override { return 0; }
359  int numSrcRegOperands() override { return 0; }
360  int instSize() const override { return 0; }
361 };
362 
363 } // namespace gem5
364 
365 #endif // __GPU_STATIC_INST_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::GPUStaticInst::initDynOperandInfo
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
Definition: gpu_static_inst.cc:60
gem5::GPUStaticInst::ipdInstNum
void ipdInstNum(int num)
Definition: gpu_static_inst.hh:76
gem5::GPUStaticInst::isReturn
bool isReturn() const
Definition: gpu_static_inst.hh:114
gem5::GPUStaticInst::dynamic_id_count
static uint64_t dynamic_id_count
Definition: gpu_static_inst.hh:240
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::GPUStaticInst::isAtomicMin
bool isAtomicMin() const
Definition: gpu_static_inst.hh:169
gem5::GPUStaticInst::isDPPInst
bool isDPPInst() const
Definition: gpu_static_inst.hh:118
gem5::GPUStaticInst::isAtomicInc
bool isAtomicInc() const
Definition: gpu_static_inst.hh:166
gem5::GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:113
gem5::GPUStaticInst::GPUStaticInst
GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:41
gem5::GPUStaticInst::DST_VEC
@ DST_VEC
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::isMAD
bool isMAD() const
Definition: gpu_static_inst.hh:220
gem5::GPUStaticInst::instAddr
int instAddr() const
Definition: gpu_static_inst.hh:69
gem5::GPUStaticInst::numSrcRegOperands
virtual int numSrcRegOperands()=0
gem5::SparcISA::Nop
Nop class.
Definition: nop.hh:48
gem5::GPUStaticInst::isAtomicMax
bool isAtomicMax() const
Definition: gpu_static_inst.hh:168
gem5::GPUStaticInst::isAtomicExch
bool isAtomicExch() const
Definition: gpu_static_inst.hh:163
gem5::GPUStaticInst::isNop
bool isNop() const
Definition: gpu_static_inst.hh:113
gem5::GPUStaticInst::_flags
std::bitset< Num_Flags > _flags
Definition: gpu_static_inst.hh:323
gem5::GPUStaticInst::isFlat
bool isFlat() const
Definition: gpu_static_inst.hh:133
gem5::GPUStaticInst::writesEXEC
bool writesEXEC() const
Definition: gpu_static_inst.hh:154
gem5::GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:49
gem5::GPUStaticInst::_instNum
int _instNum
Definition: gpu_static_inst.hh:301
gem5::GPUStaticInst::isScalar
bool isScalar() const
Definition: gpu_static_inst.hh:146
gem5::Wavefront
Definition: wavefront.hh:62
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:300
gem5::GPUStaticInst::srcOps
std::vector< OperandInfo > srcOps
Definition: gpu_static_inst.hh:303
gem5::GPUStaticInst::isAtomicNoRet
bool isAtomicNoRet() const
Definition: gpu_static_inst.hh:143
gem5::GPUStaticInst::isGroupSeg
bool isGroupSeg() const
Definition: gpu_static_inst.hh:193
gem5::GPUStaticInst::initiateAcc
virtual void initiateAcc(GPUDynInstPtr gpuDynInst)
Definition: gpu_static_inst.hh:226
gem5::GPUStaticInst::srcVecDWords
int srcVecDWords
Definition: gpu_static_inst.hh:307
misc.hh
gem5::GPUStaticInst::isWaitcnt
bool isWaitcnt() const
Definition: gpu_static_inst.hh:127
gem5::KernelLaunchStaticInst::generateDisassembly
void generateDisassembly() override
Definition: gpu_static_inst.hh:345
gem5::GPUStaticInst::writesVCC
bool writesVCC() const
Definition: gpu_static_inst.hh:150
gem5::GPUStaticInst::executed_as
enums::StorageClassType executed_as
Definition: gpu_static_inst.hh:243
gem5::GPUStaticInst::srcScalarRegOperands
const std::vector< OperandInfo > & srcScalarRegOperands() const
Definition: gpu_static_inst.hh:282
std::vector
STL vector class.
Definition: stl.hh:37
gem5::GPUStaticInst::isMemSync
bool isMemSync() const
Definition: gpu_static_inst.hh:131
gem5::GPUStaticInst::dstVecRegOperands
const std::vector< OperandInfo > & dstVecRegOperands() const
Definition: gpu_static_inst.hh:276
gem5::GPUStaticInst::isSDWAInst
bool isSDWAInst() const
Definition: gpu_static_inst.hh:117
gem5::GPUStaticInst::nextInstAddr
int nextInstAddr() const
Definition: gpu_static_inst.hh:70
gem5::GPUStaticInst::isFMA
bool isFMA() const
Definition: gpu_static_inst.hh:218
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::KernelLaunchStaticInst::initOperandInfo
void initOperandInfo() override
Definition: gpu_static_inst.hh:350
gem5::GPUStaticInst::isGloballyCoherent
bool isGloballyCoherent() const
Coherence domain of a memory instruction.
Definition: gpu_static_inst.hh:209
gem5::GPUStaticInst::SRC_VEC
@ SRC_VEC
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:119
wavefront.hh
gem5::KernelLaunchStaticInst::isFlatScratchRegister
bool isFlatScratchRegister(int opIdx) override
Definition: gpu_static_inst.hh:352
gem5::GPUStaticInst::instNum
void instNum(int num)
Definition: gpu_static_inst.hh:72
gem5::GPUStaticInst::isStore
bool isStore() const
Definition: gpu_static_inst.hh:135
gem5::GPUStaticInst::isALU
bool isALU() const
Definition: gpu_static_inst.hh:110
gem5::GPUStaticInst::srcScalarRegOps
std::vector< OperandInfo > srcScalarRegOps
Definition: gpu_static_inst.hh:315
Nop
def format Nop(code, *opt_flags)
Definition: nop.cc:82
gem5::GPUStaticInst::isAtomicRet
bool isAtomicRet() const
Definition: gpu_static_inst.hh:144
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:264
gem5::GPUStaticInst::isEndOfKernel
bool isEndOfKernel() const
Definition: gpu_static_inst.hh:115
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::Flags
Wrapper that groups a few flag bits under the same undelying container.
Definition: flags.hh:44
gem5::GPUStaticInst::readsMode
bool readsMode() const
Definition: gpu_static_inst.hh:155
gem5::GPUStaticInst::DST_SCALAR
@ DST_SCALAR
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::isBarrier
bool isBarrier() const
Definition: gpu_static_inst.hh:130
gem5::GPUStaticInst::isF16
bool isF16() const
Definition: gpu_static_inst.hh:213
gem5::GPUStaticInst::numDstScalarDWords
int numDstScalarDWords()
Definition: gpu_static_inst.cc:184
gem5::GPUStaticInst::isBranch
bool isBranch() const
Definition: gpu_static_inst.hh:111
gem5::GPUStaticInst::isFlatScratchRegister
virtual bool isFlatScratchRegister(int opIdx)=0
gem5::GPUStaticInst::execute
virtual void execute(GPUDynInstPtr gpuDynInst)=0
gem5::GPUStaticInst::isAtomicSub
bool isAtomicSub() const
Definition: gpu_static_inst.hh:165
gem5::GPUStaticInst::maxOperandSize
int maxOperandSize()
Definition: gpu_static_inst.cc:199
gem5::RiscvISA::Load
Definition: mem.hh:56
gem5::GPUStaticInst::writesMode
bool writesMode() const
Definition: gpu_static_inst.hh:156
gem5::GPUStaticInst::getNumOperands
virtual int getNumOperands()=0
gem5::GPUStaticInst::srcLiteral
virtual TheGpuISA::ScalarRegU32 srcLiteral() const
Definition: gpu_static_inst.hh:80
gem5::GPUStaticInst::numDstVecDWords
int numDstVecDWords()
Definition: gpu_static_inst.cc:141
gem5::GPUStaticInst::isAtomicDec
bool isAtomicDec() const
Definition: gpu_static_inst.hh:167
gem5::GPUStaticInst::srcVecRegOperands
const std::vector< OperandInfo > & srcVecRegOperands() const
Definition: gpu_static_inst.hh:270
gem5::GPUStaticInst::dstOps
std::vector< OperandInfo > dstOps
Definition: gpu_static_inst.hh:304
gem5::KernelLaunchStaticInst::KernelLaunchStaticInst
KernelLaunchStaticInst()
Definition: gpu_static_inst.hh:329
gpu_dyn_inst.hh
gem5::GPUStaticInst::dstScalarRegOperands
const std::vector< OperandInfo > & dstScalarRegOperands() const
Definition: gpu_static_inst.hh:288
gem5::GPUStaticInst::isMAC
bool isMAC() const
Definition: gpu_static_inst.hh:219
gem5::GPUStaticInst::numDstScalarOperands
int numDstScalarOperands()
Definition: gpu_static_inst.cc:163
gem5::GPUStaticInst::isAtomicCAS
bool isAtomicCAS() const
Definition: gpu_static_inst.hh:162
gem5::GPUStaticInst::instSize
virtual int instSize() const =0
gem5::KernelLaunchStaticInst::getNumOperands
int getNumOperands() override
Definition: gpu_static_inst.hh:351
gem5::GPUStaticInst::isReadOnlySeg
bool isReadOnlySeg() const
Definition: gpu_static_inst.hh:196
gem5::GPUStaticInst::numSrcScalarDWords
int numSrcScalarDWords()
Definition: gpu_static_inst.cc:169
gem5::KernelLaunchStaticInst::execute
void execute(GPUDynInstPtr gpuDynInst) override
Definition: gpu_static_inst.hh:339
gem5::GPUStaticInst::generateDisassembly
virtual void generateDisassembly()=0
gem5::GPUStaticInst::_ipdInstNum
int _ipdInstNum
Identifier of the immediate post-dominator instruction.
Definition: gpu_static_inst.hh:321
gem5::GPUStaticInst::readsVCC
bool readsVCC() const
Definition: gpu_static_inst.hh:149
gem5::GPUStaticInst::MapRegFn
int(RegisterManager::* MapRegFn)(Wavefront *, int)
Definition: gpu_static_inst.hh:295
gem5::GPUStaticInst::isLoad
bool isLoad() const
Definition: gpu_static_inst.hh:134
gem5::GPUStaticInst::OpType
OpType
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::srcOperands
const std::vector< OperandInfo > & srcOperands() const
Definition: gpu_static_inst.hh:266
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
gem5::GPUStaticInst::isKernArgSeg
bool isKernArgSeg() const
Definition: gpu_static_inst.hh:194
gem5::GPUStaticInst::_instAddr
int _instAddr
Definition: gpu_static_inst.hh:302
gem5::GPUStaticInst::dstOperands
const std::vector< OperandInfo > & dstOperands() const
Definition: gpu_static_inst.hh:267
gem5::GPUStaticInst::getTargetPc
virtual uint32_t getTargetPc()
Definition: gpu_static_inst.hh:238
gem5::GPUStaticInst::isAtomicAdd
bool isAtomicAdd() const
Definition: gpu_static_inst.hh:164
gem5::GPUStaticInst::isUnconditionalJump
bool isUnconditionalJump() const
Definition: gpu_static_inst.hh:121
gem5::GPUStaticInst::isKernelLaunch
bool isKernelLaunch() const
Definition: gpu_static_inst.hh:116
gem5::GPUStaticInst::isF32
bool isF32() const
Definition: gpu_static_inst.hh:214
gem5::RiscvISA::Store
Definition: mem.hh:65
gem5::GPUStaticInst::isF64
bool isF64() const
Definition: gpu_static_inst.hh:215
gem5::KernelLaunchStaticInst::numDstRegOperands
int numDstRegOperands() override
Definition: gpu_static_inst.hh:358
gem5::GPUStaticInst::instNum
int instNum()
Definition: gpu_static_inst.hh:74
gem5::GPUStaticInst::writesSCC
bool writesSCC() const
Definition: gpu_static_inst.hh:148
gem5::KernelLaunchStaticInst::getOperandSize
int getOperandSize(int operandIndex) override
Definition: gpu_static_inst.hh:356
gem5::GPUStaticInst::_opcode
const std::string _opcode
Definition: gpu_static_inst.hh:299
gem5::GPUStaticInst::isSpillSeg
bool isSpillSeg() const
Definition: gpu_static_inst.hh:197
gem5::KernelLaunchStaticInst::numSrcRegOperands
int numSrcRegOperands() override
Definition: gpu_static_inst.hh:359
gem5::KernelLaunchStaticInst::instSize
int instSize() const override
Definition: gpu_static_inst.hh:360
gem5::GPUStaticInst::isSystemCoherent
bool isSystemCoherent() const
Definition: gpu_static_inst.hh:210
gem5::SparcISA::Branch
Base class for branch operations.
Definition: branch.hh:48
gem5::GPUStaticInst::isAtomicOr
bool isAtomicOr() const
Definition: gpu_static_inst.hh:160
gem5::GPUStaticInst::numSrcScalarOperands
int numSrcScalarOperands()
Definition: gpu_static_inst.cc:157
gem5::GPUStaticInst::SRC_SCALAR
@ SRC_SCALAR
Definition: gpu_static_inst.hh:296
gem5::GPUStaticInst::isGlobalMem
bool isGlobalMem() const
Definition: gpu_static_inst.hh:178
gem5::GPUStaticInst::readsEXEC
bool readsEXEC() const
Definition: gpu_static_inst.hh:153
gem5::GPUStaticInst::ipdInstNum
int ipdInstNum() const
Definition: gpu_static_inst.hh:78
gem5::GPUStaticInst::srcScalarDWords
int srcScalarDWords
Definition: gpu_static_inst.hh:309
gem5::KernelLaunchStaticInst::isExecMaskRegister
bool isExecMaskRegister(int opIdx) override
Definition: gpu_static_inst.hh:355
gem5::GPUStaticInst::dstScalarRegOps
std::vector< OperandInfo > dstScalarRegOps
Definition: gpu_static_inst.hh:316
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Definition: gpu_static_inst.hh:67
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Definition: gpu_static_inst.hh:233
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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