gem5  v22.1.0.0
gpu_static_inst.hh
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31 
32 #ifndef __GPU_STATIC_INST_HH__
33 #define __GPU_STATIC_INST_HH__
34 
35 /*
36  * @file gpu_static_inst.hh
37  *
38  * Defines the base class representing static instructions for the GPU. The
39  * instructions are "static" because they contain no dynamic instruction
40  * information. GPUStaticInst corresponds to the StaticInst class for the CPU
41  * models.
42  */
43 
44 #include <cstdint>
45 #include <string>
46 #include <vector>
47 
48 #include "enums/GPUStaticInstFlags.hh"
49 #include "enums/StorageClassType.hh"
51 #include "gpu-compute/misc.hh"
53 #include "gpu-compute/wavefront.hh"
54 
55 namespace gem5
56 {
57 
58 class BaseOperand;
59 class BaseRegOperand;
60 
61 class GPUStaticInst : public GPUStaticInstFlags
62 {
63  public:
64  GPUStaticInst(const std::string &opcode);
65  virtual ~GPUStaticInst() { }
66  void instAddr(int inst_addr) { _instAddr = inst_addr; }
67  int instAddr() const { return _instAddr; }
68  int nextInstAddr() const { return _instAddr + instSize(); }
69 
70  void instNum(int num) { _instNum = num; }
71 
72  int instNum() { return _instNum; }
73 
74  void ipdInstNum(int num) { _ipdInstNum = num; }
75 
76  int ipdInstNum() const { return _ipdInstNum; }
77 
78  virtual TheGpuISA::ScalarRegU32 srcLiteral() const { return 0; }
79 
81 
82  virtual void initOperandInfo() = 0;
83  virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
84  virtual void generateDisassembly() = 0;
85  const std::string& disassemble();
86  virtual int getNumOperands() = 0;
87  virtual bool isFlatScratchRegister(int opIdx) = 0;
88  virtual bool isExecMaskRegister(int opIdx) = 0;
89  virtual int getOperandSize(int operandIndex) = 0;
90 
91  virtual int numDstRegOperands() = 0;
92  virtual int numSrcRegOperands() = 0;
93 
94  int numSrcVecOperands();
95  int numDstVecOperands();
96  int numSrcVecDWords();
97  int numDstVecDWords();
98 
100  int numDstScalarOperands();
101  int numSrcScalarDWords();
102  int numDstScalarDWords();
103 
104  int maxOperandSize();
105 
106  virtual int coalescerTokenCount() const { return 0; }
107 
108  bool isALU() const { return _flags[ALU]; }
109  bool isBranch() const { return _flags[Branch]; }
110  bool isCondBranch() const { return _flags[CondBranch]; }
111  bool isNop() const { return _flags[Nop]; }
112  bool isReturn() const { return _flags[Return]; }
113  bool isEndOfKernel() const { return _flags[EndOfKernel]; }
114  bool isKernelLaunch() const { return _flags[KernelLaunch]; }
115  bool isSDWAInst() const { return _flags[IsSDWA]; }
116  bool isDPPInst() const { return _flags[IsDPP]; }
117 
118  bool
120  {
121  return _flags[UnconditionalJump];
122  }
123 
124  bool isSpecialOp() const { return _flags[SpecialOp]; }
125  bool isWaitcnt() const { return _flags[Waitcnt]; }
126  bool isSleep() const { return _flags[Sleep]; }
127 
128  bool isBarrier() const { return _flags[MemBarrier]; }
129  bool isMemSync() const { return _flags[MemSync]; }
130  bool isMemRef() const { return _flags[MemoryRef]; }
131  bool isFlat() const { return _flags[Flat]; }
132  bool isFlatGlobal() const { return _flags[FlatGlobal]; }
133  bool isLoad() const { return _flags[Load]; }
134  bool isStore() const { return _flags[Store]; }
135 
136  bool
137  isAtomic() const
138  {
139  return _flags[AtomicReturn] || _flags[AtomicNoReturn];
140  }
141 
142  bool isAtomicNoRet() const { return _flags[AtomicNoReturn]; }
143  bool isAtomicRet() const { return _flags[AtomicReturn]; }
144 
145  bool isScalar() const { return _flags[Scalar]; }
146  bool readsSCC() const { return _flags[ReadsSCC]; }
147  bool writesSCC() const { return _flags[WritesSCC]; }
148  bool readsVCC() const { return _flags[ReadsVCC]; }
149  bool writesVCC() const { return _flags[WritesVCC]; }
150  // Identify instructions that implicitly read the Execute mask
151  // as a source operand but not to dictate which threads execute.
152  bool readsEXEC() const { return _flags[ReadsEXEC]; }
153  bool writesEXEC() const { return _flags[WritesEXEC]; }
154  bool readsMode() const { return _flags[ReadsMode]; }
155  bool writesMode() const { return _flags[WritesMode]; }
156  bool ignoreExec() const { return _flags[IgnoreExec]; }
157 
158  bool isAtomicAnd() const { return _flags[AtomicAnd]; }
159  bool isAtomicOr() const { return _flags[AtomicOr]; }
160  bool isAtomicXor() const { return _flags[AtomicXor]; }
161  bool isAtomicCAS() const { return _flags[AtomicCAS]; }
162  bool isAtomicExch() const { return _flags[AtomicExch]; }
163  bool isAtomicAdd() const { return _flags[AtomicAdd]; }
164  bool isAtomicSub() const { return _flags[AtomicSub]; }
165  bool isAtomicInc() const { return _flags[AtomicInc]; }
166  bool isAtomicDec() const { return _flags[AtomicDec]; }
167  bool isAtomicMax() const { return _flags[AtomicMax]; }
168  bool isAtomicMin() const { return _flags[AtomicMin]; }
169 
170  bool
171  isArgLoad() const
172  {
173  return (_flags[KernArgSegment] || _flags[ArgSegment]) && _flags[Load];
174  }
175 
176  bool
177  isGlobalMem() const
178  {
179  return _flags[MemoryRef] && (_flags[GlobalSegment] ||
180  _flags[PrivateSegment] || _flags[ReadOnlySegment] ||
181  _flags[SpillSegment] || _flags[FlatGlobal]);
182  }
183 
184  bool
185  isLocalMem() const
186  {
187  return _flags[MemoryRef] && _flags[GroupSegment];
188  }
189 
190  bool isArgSeg() const { return _flags[ArgSegment]; }
191  bool isGlobalSeg() const { return _flags[GlobalSegment]; }
192  bool isGroupSeg() const { return _flags[GroupSegment]; }
193  bool isKernArgSeg() const { return _flags[KernArgSegment]; }
194  bool isPrivateSeg() const { return _flags[PrivateSegment]; }
195  bool isReadOnlySeg() const { return _flags[ReadOnlySegment]; }
196  bool isSpillSeg() const { return _flags[SpillSegment]; }
197 
208  bool isGloballyCoherent() const { return _flags[GloballyCoherent]; }
209  bool isSystemCoherent() const { return _flags[SystemCoherent]; }
210 
211  // Floating-point instructions
212  bool isF16() const { return _flags[F16]; }
213  bool isF32() const { return _flags[F32]; }
214  bool isF64() const { return _flags[F64]; }
215 
216  // FMA, MAC, MAD instructions
217  bool isFMA() const { return _flags[FMA]; }
218  bool isMAC() const { return _flags[MAC]; }
219  bool isMAD() const { return _flags[MAD]; }
220 
221  virtual int instSize() const = 0;
222 
223  // only used for memory instructions
224  virtual void
226  {
227  fatal("calling initiateAcc() on a non-memory instruction.\n");
228  }
229 
230  // only used for memory instructions
231  virtual void
233  {
234  fatal("calling completeAcc() on a non-memory instruction.\n");
235  }
236 
237  virtual uint32_t getTargetPc() { return 0; }
238 
239  static uint64_t dynamic_id_count;
240 
241  // For flat memory accesses
242  enums::StorageClassType executed_as;
243 
244  void setFlag(Flags flag) {
245  _flags[flag] = true;
246 
247  if (isGroupSeg()) {
248  executed_as = enums::SC_GROUP;
249  } else if (isGlobalSeg()) {
250  executed_as = enums::SC_GLOBAL;
251  } else if (isPrivateSeg()) {
252  executed_as = enums::SC_PRIVATE;
253  } else if (isSpillSeg()) {
254  executed_as = enums::SC_SPILL;
255  } else if (isReadOnlySeg()) {
256  executed_as = enums::SC_READONLY;
257  } else if (isKernArgSeg()) {
258  executed_as = enums::SC_KERNARG;
259  } else if (isArgSeg()) {
260  executed_as = enums::SC_ARG;
261  }
262  }
263  const std::string& opcode() const { return _opcode; }
264 
265  const std::vector<OperandInfo>& srcOperands() const { return srcOps; }
266  const std::vector<OperandInfo>& dstOperands() const { return dstOps; }
267 
270  {
271  return srcVecRegOps;
272  }
273 
276  {
277  return dstVecRegOps;
278  }
279 
282  {
283  return srcScalarRegOps;
284  }
285 
288  {
289  return dstScalarRegOps;
290  }
291 
292  // These next 2 lines are used in initDynOperandInfo to let the lambda
293  // function work
294  typedef int (RegisterManager::*MapRegFn)(Wavefront *, int);
296 
297  protected:
298  const std::string _opcode;
299  std::string disassembly;
300  int _instNum;
304 
305  private:
311 
316 
321 
322  std::bitset<Num_Flags> _flags;
323 };
324 
326 {
327  public:
329  {
330  setFlag(Nop);
331  setFlag(KernelLaunch);
332  setFlag(MemSync);
333  setFlag(Scalar);
334  setFlag(GlobalSegment);
335  }
336 
337  void
338  execute(GPUDynInstPtr gpuDynInst) override
339  {
340  fatal("kernel launch instruction should not be executed\n");
341  }
342 
343  void
345  {
347  }
348 
349  void initOperandInfo() override { return; }
350  int getNumOperands() override { return 0; }
351  bool isFlatScratchRegister(int opIdx) override { return false; }
352  // return true if the Execute mask is explicitly used as a source
353  // register operand
354  bool isExecMaskRegister(int opIdx) override { return false; }
355  int getOperandSize(int operandIndex) override { return 0; }
356 
357  int numDstRegOperands() override { return 0; }
358  int numSrcRegOperands() override { return 0; }
359  int instSize() const override { return 0; }
360 };
361 
362 } // namespace gem5
363 
364 #endif // __GPU_STATIC_INST_HH__
Wrapper that groups a few flag bits under the same undelying container.
Definition: flags.hh:45
virtual int numDstRegOperands()=0
const std::vector< OperandInfo > & srcScalarRegOperands() const
bool isGlobalMem() const
std::bitset< Num_Flags > _flags
virtual TheGpuISA::ScalarRegU32 srcLiteral() const
bool isAtomicDec() const
bool isGloballyCoherent() const
Coherence domain of a memory instruction.
std::vector< OperandInfo > srcOps
const std::string & opcode() const
const std::string & disassemble()
void setFlag(Flags flag)
bool isSpecialOp() const
bool isReadOnlySeg() const
std::vector< OperandInfo > dstScalarRegOps
enums::StorageClassType executed_as
virtual void generateDisassembly()=0
bool isPrivateSeg() const
virtual int getOperandSize(int operandIndex)=0
bool isGlobalSeg() const
bool isAtomicSub() const
const std::vector< OperandInfo > & srcVecRegOperands() const
virtual bool isExecMaskRegister(int opIdx)=0
const std::vector< OperandInfo > & srcOperands() const
bool isAtomicMin() const
void ipdInstNum(int num)
GPUStaticInst(const std::string &opcode)
std::vector< OperandInfo > dstVecRegOps
int _ipdInstNum
Identifier of the immediate post-dominator instruction.
std::vector< OperandInfo > dstOps
static uint64_t dynamic_id_count
bool isKernArgSeg() const
bool isEndOfKernel() const
bool isCondBranch() const
int nextInstAddr() const
virtual bool isFlatScratchRegister(int opIdx)=0
bool isAtomicInc() const
bool isKernelLaunch() const
void instNum(int num)
bool isAtomicMax() const
bool isAtomicCAS() const
bool isFlatGlobal() const
bool isSystemCoherent() const
virtual void initOperandInfo()=0
virtual void execute(GPUDynInstPtr gpuDynInst)=0
const std::vector< OperandInfo > & dstVecRegOperands() const
virtual void completeAcc(GPUDynInstPtr gpuDynInst)
std::vector< OperandInfo > srcVecRegOps
bool isAtomicRet() const
const std::vector< OperandInfo > & dstScalarRegOperands() const
virtual int getNumOperands()=0
bool isAtomicAdd() const
virtual uint32_t getTargetPc()
virtual int instSize() const =0
std::vector< OperandInfo > srcScalarRegOps
bool isAtomicExch() const
const std::string _opcode
bool isAtomicNoRet() const
virtual int coalescerTokenCount() const
bool isUnconditionalJump() const
void instAddr(int inst_addr)
virtual void initiateAcc(GPUDynInstPtr gpuDynInst)
void initDynOperandInfo(Wavefront *wf, ComputeUnit *cu)
virtual int numSrcRegOperands()=0
bool isAtomicXor() const
bool isAtomicAnd() const
const std::vector< OperandInfo > & dstOperands() const
int(RegisterManager::* MapRegFn)(Wavefront *, int)
bool isFlatScratchRegister(int opIdx) override
int getOperandSize(int operandIndex) override
void execute(GPUDynInstPtr gpuDynInst) override
int instSize() const override
bool isExecMaskRegister(int opIdx) override
Base class for branch operations.
Definition: branch.hh:49
Nop class.
Definition: nop.hh:49
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1931
STL vector class.
Definition: stl.hh:37
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
uint32_t ScalarRegU32
constexpr RegId F16
Definition: float.hh:115
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
def format Nop(code, *opt_flags)
Definition: nop.cc:82

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