gem5 v24.0.0.0
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gpu_registers.hh
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1/*
2 * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __ARCH_VEGA_REGISTERS_HH__
33#define __ARCH_VEGA_REGISTERS_HH__
34
35#include <array>
36#include <cstdint>
37#include <string>
38
40#include "base/intmath.hh"
41#include "base/logging.hh"
42
43namespace gem5
44{
45
46namespace VegaISA
47{
48 enum OpSelector : int
49 {
74 REG_M0 = 124,
78 REG_ZERO = 128,
122 REG_PI = 248,
123 /* NOTE: SDWA and SWDA both refer to sub d-word addressing */
126 REG_VCCZ = 251,
128 REG_SCC = 253,
132 REG_VGPR_MAX = 767
133 };
134
135 constexpr size_t MaxOperandDwords(16);
136 const int NumVecElemPerVecReg(64);
137 // op selector values 129 - 192 correspond to const values 1 - 64
140 // op selector values 193 - 208 correspond to const values -1 - 16
143 const int BITS_PER_BYTE = 8;
144 const int BITS_PER_WORD = 16;
145 const int MSB_PER_BYTE = (BITS_PER_BYTE - 1);
146 const int MSB_PER_WORD = (BITS_PER_WORD - 1);
147
148 // typedefs for the various sizes/types of scalar regs
149 typedef uint8_t ScalarRegU8;
150 typedef int8_t ScalarRegI8;
151 typedef uint16_t ScalarRegU16;
152 typedef int16_t ScalarRegI16;
153 typedef uint32_t ScalarRegU32;
154 typedef int32_t ScalarRegI32;
155 typedef float ScalarRegF32;
156 typedef uint64_t ScalarRegU64;
157 typedef int64_t ScalarRegI64;
158 typedef double ScalarRegF64;
159
160 // typedefs for the various sizes/types of vector reg elements
161 typedef uint8_t VecElemU8;
162 typedef int8_t VecElemI8;
163 typedef uint16_t VecElemU16;
164 typedef int16_t VecElemI16;
165 typedef uint32_t VecElemU32;
166 typedef int32_t VecElemI32;
167 typedef float VecElemF32;
168 typedef uint64_t VecElemU64;
169 typedef int64_t VecElemI64;
170 typedef double VecElemF64;
171
172 const int DWordSize = sizeof(VecElemU32);
176 const int RegSizeDWords = sizeof(VecElemU32) / DWordSize;
177
182
184 {
185 StatusReg() : SCC(0), SPI_PRIO(0), USER_PRIO(0), PRIV(0), TRAP_EN(0),
186 TTRACE_EN(0), EXPORT_RDY(0), EXECZ(0), VCCZ(0), IN_TG(0),
187 IN_BARRIER(0), HALT(0), TRAP(0), TTRACE_CU_EN(0), VALID(0),
191 {
192 }
193
194 uint32_t SCC : 1;
195 uint32_t SPI_PRIO : 2;
196 uint32_t USER_PRIO : 2;
197 uint32_t PRIV : 1;
198 uint32_t TRAP_EN : 1;
199 uint32_t TTRACE_EN : 1;
200 uint32_t EXPORT_RDY : 1;
201 uint32_t EXECZ : 1;
202 uint32_t VCCZ : 1;
203 uint32_t IN_TG : 1;
204 uint32_t IN_BARRIER : 1;
205 uint32_t HALT : 1;
206 uint32_t TRAP : 1;
207 uint32_t TTRACE_CU_EN : 1;
208 uint32_t VALID : 1;
209 uint32_t ECC_ERR : 1;
210 uint32_t SKIP_EXPORT : 1;
211 uint32_t PERF_EN : 1;
212 uint32_t COND_DBG_USER : 1;
213 uint32_t COND_DBG_SYS : 1;
214 uint32_t ALLOW_REPLAY : 1;
215 uint32_t INSTRUCTION_ATC : 1;
216 uint32_t RESERVED : 3;
217 uint32_t MUST_EXPORT : 1;
218 uint32_t RESERVED_1 : 4;
219 };
220
221 std::string opSelectorToRegSym(int opIdx, int numRegs=0);
222 int opSelectorToRegIdx(int opIdx, int numScalarRegs);
223 bool isPosConstVal(int opIdx);
224 bool isNegConstVal(int opIdx);
225 bool isConstVal(int opIdx);
226 bool isLiteral(int opIdx);
227 bool isScalarReg(int opIdx);
228 bool isVectorReg(int opIdx);
229 bool isFlatScratchReg(int opIdx);
230 bool isExecMask(int opIdx);
231 bool isVccReg(int opIdx);
232} // namespace VegaISA
233} // namespace gem5
234
235#endif // __ARCH_VEGA_REGISTERS_HH__
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition vec_reg.hh:126
constexpr unsigned NumVecElemPerVecReg
Definition vec.hh:61
bool isVectorReg(int opIdx)
const int NumPosConstRegs
const int DWordSize
const int RegSizeDWords
Size of a single-precision register in DWords.
bool isNegConstVal(int opIdx)
int opSelectorToRegIdx(int idx, int numScalarRegs)
uint64_t ScalarRegU64
uint16_t VecElemU16
const int BITS_PER_WORD
uint16_t ScalarRegU16
bool isVccReg(int opIdx)
const int MSB_PER_BYTE
bool isConstVal(int opIdx)
uint32_t VecElemU32
bool isLiteral(int opIdx)
bool isScalarReg(int opIdx)
uint64_t VecElemU64
const int MSB_PER_WORD
const int BITS_PER_BYTE
std::string opSelectorToRegSym(int idx, int numRegs)
constexpr size_t MaxOperandDwords(16)
bool isFlatScratchReg(int opIdx)
bool isPosConstVal(int opIdx)
const int NumNegConstRegs
bool isExecMask(int opIdx)
uint32_t ScalarRegU32
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Vector Registers layout specification.

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