gem5 v24.1.0.1
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classes that represnt vector/scalar operands in VEGA ISA. More...
Functions | |
std::string | opSelectorToRegSym (int idx, int numRegs) |
int | opSelectorToRegIdx (int idx, int numScalarRegs) |
bool | isPosConstVal (int opIdx) |
bool | isNegConstVal (int opIdx) |
bool | isConstVal (int opIdx) |
bool | isLiteral (int opIdx) |
bool | isExecMask (int opIdx) |
bool | isVccReg (int opIdx) |
bool | isFlatScratchReg (int opIdx) |
bool | isScalarReg (int opIdx) |
bool | isVectorReg (int opIdx) |
constexpr size_t | MaxOperandDwords (16) |
const int | NumVecElemPerVecReg (64) |
template<typename T > | |
T | wholeQuadMode (T val) |
template<typename T > | |
T | quadMask (T val) |
template<typename T > | |
ScalarRegI32 | countZeroBits (T val) |
template<typename T > | |
ScalarRegI32 | findFirstZero (T val) |
template<typename T > | |
ScalarRegI32 | findFirstOne (T val) |
template<typename T > | |
ScalarRegI32 | findFirstOneMsb (T val) |
template<typename T > | |
ScalarRegI32 | countZeroBitsMsb (T val) |
ScalarRegI32 | firstOppositeSignBit (ScalarRegI32 val) |
ScalarRegI32 | firstOppositeSignBit (ScalarRegI64 val) |
template<typename T > | |
T | median (T val_0, T val_1, T val_2) |
template<typename T > | |
T | roundNearestEven (T val) |
VecElemU32 | muladd (VecElemU64 &dst, VecElemU32 val_0, VecElemU32 val_1, VecElemU64 val_2) |
VecElemU32 | muladd (VecElemI64 &dst, VecElemI32 val_0, VecElemI32 val_1, VecElemI64 val_2) |
int | dppInstImpl (SqDPPVals dppCtrl, int currLane, int rowNum, int rowOffset, bool &outOfBounds) |
dppInstImpl is a helper function that performs the inputted operation on the inputted vector register lane. | |
template<typename T > | |
void | processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0) |
processDPP is a helper function for implementing Data Parallel Primitive instructions. | |
template<typename T > | |
void | processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0, T &src1) |
processDPP is a helper function for implementing Data Parallel Primitive instructions. | |
template<typename T > | |
T | sdwaInstSrcImpl_helper (T currOperVal, const T origOperVal, const SDWASelVals sel, const bool signExt) |
sdwaInstSrcImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. | |
template<typename T > | |
void | sdwaInstSrcImpl (T &currOper, T &origCurrOper, const SDWASelVals sel, const bool signExt) |
sdwaInstSrcImpl is a helper function that selects the appropriate bits/bytes for each lane of the inputted source operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. | |
template<typename T > | |
T | sdwaInstDstImpl_helper (T currDstVal, const T origDstVal, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format) |
sdwaInstDstImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. | |
template<typename T > | |
void | sdwaInstDstImpl (T &dstOper, T &origDstOper, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format) |
sdwaInstDestImpl is a helper function that selects the appropriate bits/bytes for the inputted dest operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. | |
template<typename T > | |
void | processSDWA_src_helper (T &currSrc, T &origCurrSrc, const SDWASelVals src_sel, const bool src_signExt, const bool src_abs, const bool src_neg) |
processSDWA_srcHelper is a helper function for implementing sub d-word addressing instructions for the src operands. | |
template<typename T > | |
void | processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0) |
processSDWA_src is a helper function for implementing sub d-word addressing instructions for the src operands. | |
template<typename T > | |
void | processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0, T &src1, T &origSrc1) |
processSDWA_src is a helper function for implementing sub d-word addressing instructions. | |
template<typename T > | |
void | processSDWA_dst (InFmt_VOP_SDWA sdwaInst, T &dst, T &origDst) |
processSDWA_dst is a helper function for implementing sub d-word addressing instructions for the dst operand. | |
template<int N> | |
int32_t | dotClampI (int32_t value, bool clamp) |
template<int N> | |
uint32_t | dotClampU (uint32_t value, bool clamp) |
int16_t | clampI16 (int32_t value, bool clamp) |
uint16_t | clampU16 (uint32_t value, bool clamp) |
uint16_t | clampF16 (uint16_t value, bool clamp) |
float | clampF32 (float value, bool clamp) |
BitUnion64 (PageTableEntry) Bitfield< 58 | |
The page table entry is reverse engineered from the macros here: | |
EndBitUnion (PageTableEntry) BitUnion64(PageDirectoryEntry) Bitfield< 63 | |
Variables | |
const int | NumPosConstRegs |
const int | NumNegConstRegs |
const int | BITS_PER_BYTE = 8 |
const int | BITS_PER_WORD = 16 |
const int | MSB_PER_BYTE = (BITS_PER_BYTE - 1) |
const int | MSB_PER_WORD = (BITS_PER_WORD - 1) |
const int | DWordSize = sizeof(VecElemU32) |
const int | RegSizeDWords = sizeof(VecElemU32) / DWordSize |
Size of a single-precision register in DWords. | |
static const char * | MNEM__V_MFMA_F32_4X4X1_16B_F32 |
static const char * | MNEM__V_MFMA_F32_32X32X1_2B_F32 |
static const char * | MNEM__V_MFMA_F32_32X32X2_F32 |
static const char * | MNEM__V_MFMA_F32_16X16X4_F32 |
static const char * | MNEM__V_MFMA_F32_16X16X1_4B_F32 |
static const char * | MNEM__V_MFMA_F64_4X4X4_4B_F64 |
static const char * | MNEM__V_MFMA_F64_16X16X4_F64 |
static const char * | MNEM__V_MFMA_F32_16X16X16_F16 |
static const char * | MNEM__V_MFMA_F32_16X16X4_4B_F16 |
static const char * | MNEM__V_MFMA_F32_32X32X4_2B_F16 |
static const char * | NMEM__V_MFMA_F32_32X32X8_F16 |
static const char * | MNEM__V_MFMA_F32_4X4X4_16B_F16 |
static const char * | MNEM__V_MFMA_F32_32X32X8_BF16 |
static const char * | MNEM__V_MFMA_I32_16X16X16_I8 |
const Addr | PageShift = 12 |
const Addr | PageBytes = 1ULL << PageShift |
m | |
Bitfield< 56 > | f |
Bitfield< 55 > | l |
Bitfield< 53, 52 > | sw |
Bitfield< 51 > | t |
Bitfield< 47, 12 > | ppn |
Bitfield< 11, 7 > | fragment |
Bitfield< 6 > | w |
Bitfield< 5 > | r |
Bitfield< 4 > | x |
Bitfield< 3 > | z |
Bitfield< 2 > | c |
Bitfield< 1 > | s |
Bitfield< 0 > | v |
blockFragmentSize | |
Bitfield< 54 > | p |
Bitfield< 47, 6 > | baseAddr |
classes that represnt vector/scalar operands in VEGA ISA.
these classes wrap the generic vector register type (i.e., src/arch/generic/vec_reg.hh) and allow them to be manipulated in ways that are unique to VEGA insts.
using gem5::VegaISA::ConstScalarOperandF32 = typedef ScalarOperand<ScalarRegF32, true> |
Definition at line 801 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandF64 = typedef ScalarOperand<ScalarRegF64, true> |
Definition at line 804 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandI16 = typedef ScalarOperand<ScalarRegI16, true, 1> |
Definition at line 798 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandI32 = typedef ScalarOperand<ScalarRegI32, true> |
Definition at line 800 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandI64 = typedef ScalarOperand<ScalarRegI64, true> |
Definition at line 803 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandI8 = typedef ScalarOperand<ScalarRegI8, true, 1> |
Definition at line 796 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU128 = typedef ScalarOperand<ScalarRegU32, true, 4> |
Definition at line 805 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU16 = typedef ScalarOperand<ScalarRegU16, true, 1> |
Definition at line 797 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU256 = typedef ScalarOperand<ScalarRegU32, true, 8> |
Definition at line 806 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU32 = typedef ScalarOperand<ScalarRegU32, true> |
Definition at line 799 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU512 = typedef ScalarOperand<ScalarRegU32, true, 16> |
Definition at line 807 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU64 = typedef ScalarOperand<ScalarRegU64, true> |
Definition at line 802 of file operand.hh.
using gem5::VegaISA::ConstScalarOperandU8 = typedef ScalarOperand<ScalarRegU8, true, 1> |
Definition at line 795 of file operand.hh.
using gem5::VegaISA::ConstVecOperandF32 = typedef VecOperand<VecElemF32, true> |
Definition at line 830 of file operand.hh.
using gem5::VegaISA::ConstVecOperandF64 = typedef VecOperand<VecElemF64, true> |
Definition at line 833 of file operand.hh.
using gem5::VegaISA::ConstVecOperandI16 = typedef VecOperand<VecElemI16, true, 1> |
Definition at line 827 of file operand.hh.
using gem5::VegaISA::ConstVecOperandI32 = typedef VecOperand<VecElemI32, true> |
Definition at line 829 of file operand.hh.
using gem5::VegaISA::ConstVecOperandI64 = typedef VecOperand<VecElemI64, true> |
Definition at line 832 of file operand.hh.
using gem5::VegaISA::ConstVecOperandI8 = typedef VecOperand<VecElemI8, true, 1> |
Definition at line 825 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU128 = typedef VecOperand<VecElemU32, true, 4> |
Definition at line 835 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU16 = typedef VecOperand<VecElemU16, true, 1> |
Definition at line 826 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU256 = typedef VecOperand<VecElemU32, true, 8> |
Definition at line 836 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU32 = typedef VecOperand<VecElemU32, true> |
Definition at line 828 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU512 = typedef VecOperand<VecElemU32, true, 16> |
Definition at line 837 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU64 = typedef VecOperand<VecElemU64, true> |
Definition at line 831 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU8 = typedef VecOperand<VecElemU8, true, 1> |
Definition at line 824 of file operand.hh.
using gem5::VegaISA::ConstVecOperandU96 = typedef VecOperand<VecElemU32, true, 3> |
Definition at line 834 of file operand.hh.
using gem5::VegaISA::half = typedef uint16_t |
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_16X16X16_F16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<16, 16, 16, 1, AMDGPU::mxfloat16, &MNEM__V_MFMA_F32_16X16X16_F16> |
Definition at line 44606 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_16X16X1_4B_F32 = typedef Inst_VOP3P_MAI__V_MFMA<1, 16, 16, 1, 4, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_16X16X1_4B_F32> |
Definition at line 44377 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_16X16X4_4B_F16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<16, 16, 4, 4, AMDGPU::mxfloat16, &MNEM__V_MFMA_F32_16X16X4_4B_F16> |
Definition at line 44612 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_16X16X4_F32 = typedef Inst_VOP3P_MAI__V_MFMA<1, 16, 16, 4, 1, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_16X16X4_F32> |
Definition at line 44371 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_32X32X1_2B_F32 = typedef Inst_VOP3P_MAI__V_MFMA<1, 32, 32, 1, 2, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_32X32X1_2B_F32> |
Definition at line 44358 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_32X32X2_F32 = typedef Inst_VOP3P_MAI__V_MFMA<1, 32, 32, 2, 1, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_32X32X2_F32> |
Definition at line 44365 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_32X32X4_2B_F16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<32, 32, 4, 2, AMDGPU::mxfloat16, &MNEM__V_MFMA_F32_32X32X4_2B_F16> |
Definition at line 44618 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_32X32X8_BF16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<32, 32, 8, 1, AMDGPU::mxbfloat16, &MNEM__V_MFMA_F32_32X32X8_BF16> |
Definition at line 44636 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_32X32X8_F16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<32, 32, 8, 1, AMDGPU::mxfloat16, &NMEM__V_MFMA_F32_32X32X8_F16> |
Definition at line 44624 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_4X4X1_16B_F32 = typedef Inst_VOP3P_MAI__V_MFMA<1, 4, 4, 1, 16, ConstVecOperandF32, VecOperandF32, &MNEM__V_MFMA_F32_4X4X1_16B_F32> |
Definition at line 44352 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F32_4X4X4_16B_F16 = typedef Inst_VOP3P_MAI__V_MFMA_MXFP<4, 4, 4, 16, AMDGPU::mxfloat16, &MNEM__V_MFMA_F32_4X4X4_16B_F16> |
Definition at line 44630 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F64_16X16X4_F64 = typedef Inst_VOP3P_MAI__V_MFMA<2, 16, 16, 4, 1, ConstVecOperandF64, VecOperandF64, &MNEM__V_MFMA_F64_16X16X4_F64> |
Definition at line 44390 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_F64_4X4X4_4B_F64 = typedef Inst_VOP3P_MAI__V_MFMA<2, 4, 4, 4, 4, ConstVecOperandF64, VecOperandF64, &MNEM__V_MFMA_F64_4X4X4_4B_F64> |
Definition at line 44384 of file instructions.hh.
using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I32_16X16X16_I8 = typedef Inst_VOP3P_MAI__V_MFMA_I8<16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8> |
Definition at line 44854 of file instructions.hh.
using gem5::VegaISA::IsaDecodeMethod = typedef GPUStaticInst*(Decoder::*)(MachInst) |
Definition at line 50 of file gpu_decoder.hh.
typedef InstFormat* gem5::VegaISA::MachInst |
used to represent the encoding of a VEGA inst.
each portion of a VEGA inst must be 1 DWORD (32b), so we use a pointer to InstFormat type (which is 32b). for the case in which we need multiple DWORDS to represnt a single inst, this pointer essentialy acts as an array of the DWORDs needed to represent the entire inst encoding.
Definition at line 61 of file gpu_types.hh.
typedef uint64_t gem5::VegaISA::RawMachInst |
used to represnt a GPU inst in its raw format.
VEGA instructions may be 32b or 64b, therefore we represent a raw inst with 64b to ensure that all of its inst data, including potential immediate values, may be represented in the worst case.
Definition at line 51 of file gpu_types.hh.
using gem5::VegaISA::ScalarOperandF32 = typedef ScalarOperand<ScalarRegF32, false> |
Definition at line 787 of file operand.hh.
using gem5::VegaISA::ScalarOperandF64 = typedef ScalarOperand<ScalarRegF64, false> |
Definition at line 790 of file operand.hh.
using gem5::VegaISA::ScalarOperandI16 = typedef ScalarOperand<ScalarRegI16, false, 1> |
Definition at line 784 of file operand.hh.
using gem5::VegaISA::ScalarOperandI32 = typedef ScalarOperand<ScalarRegI32, false> |
Definition at line 786 of file operand.hh.
using gem5::VegaISA::ScalarOperandI64 = typedef ScalarOperand<ScalarRegI64, false> |
Definition at line 789 of file operand.hh.
using gem5::VegaISA::ScalarOperandI8 = typedef ScalarOperand<ScalarRegI8, false, 1> |
Definition at line 782 of file operand.hh.
using gem5::VegaISA::ScalarOperandU128 = typedef ScalarOperand<ScalarRegU32, false, 4> |
Definition at line 791 of file operand.hh.
using gem5::VegaISA::ScalarOperandU16 = typedef ScalarOperand<ScalarRegU16, false, 1> |
Definition at line 783 of file operand.hh.
using gem5::VegaISA::ScalarOperandU256 = typedef ScalarOperand<ScalarRegU32, false, 8> |
Definition at line 792 of file operand.hh.
using gem5::VegaISA::ScalarOperandU32 = typedef ScalarOperand<ScalarRegU32, false> |
Definition at line 785 of file operand.hh.
using gem5::VegaISA::ScalarOperandU512 = typedef ScalarOperand<ScalarRegU32, false, 16> |
Definition at line 793 of file operand.hh.
using gem5::VegaISA::ScalarOperandU64 = typedef ScalarOperand<ScalarRegU64, false> |
Definition at line 788 of file operand.hh.
using gem5::VegaISA::ScalarOperandU8 = typedef ScalarOperand<ScalarRegU8, false, 1> |
Definition at line 781 of file operand.hh.
typedef float gem5::VegaISA::ScalarRegF32 |
Definition at line 155 of file gpu_registers.hh.
typedef double gem5::VegaISA::ScalarRegF64 |
Definition at line 158 of file gpu_registers.hh.
typedef int16_t gem5::VegaISA::ScalarRegI16 |
Definition at line 152 of file gpu_registers.hh.
typedef int32_t gem5::VegaISA::ScalarRegI32 |
Definition at line 154 of file gpu_registers.hh.
typedef int64_t gem5::VegaISA::ScalarRegI64 |
Definition at line 157 of file gpu_registers.hh.
typedef int8_t gem5::VegaISA::ScalarRegI8 |
Definition at line 150 of file gpu_registers.hh.
typedef uint16_t gem5::VegaISA::ScalarRegU16 |
Definition at line 151 of file gpu_registers.hh.
typedef uint32_t gem5::VegaISA::ScalarRegU32 |
Definition at line 153 of file gpu_registers.hh.
typedef uint64_t gem5::VegaISA::ScalarRegU64 |
Definition at line 156 of file gpu_registers.hh.
typedef uint8_t gem5::VegaISA::ScalarRegU8 |
Definition at line 149 of file gpu_registers.hh.
typedef float gem5::VegaISA::VecElemF32 |
Definition at line 167 of file gpu_registers.hh.
typedef double gem5::VegaISA::VecElemF64 |
Definition at line 170 of file gpu_registers.hh.
typedef int16_t gem5::VegaISA::VecElemI16 |
Definition at line 164 of file gpu_registers.hh.
typedef int32_t gem5::VegaISA::VecElemI32 |
Definition at line 166 of file gpu_registers.hh.
typedef int64_t gem5::VegaISA::VecElemI64 |
Definition at line 169 of file gpu_registers.hh.
typedef int8_t gem5::VegaISA::VecElemI8 |
Definition at line 162 of file gpu_registers.hh.
typedef uint16_t gem5::VegaISA::VecElemU16 |
Definition at line 163 of file gpu_registers.hh.
typedef uint32_t gem5::VegaISA::VecElemU32 |
Definition at line 165 of file gpu_registers.hh.
typedef uint64_t gem5::VegaISA::VecElemU64 |
Definition at line 168 of file gpu_registers.hh.
typedef uint8_t gem5::VegaISA::VecElemU8 |
Definition at line 161 of file gpu_registers.hh.
using gem5::VegaISA::VecOperandF32 = typedef VecOperand<VecElemF32, false> |
Definition at line 815 of file operand.hh.
using gem5::VegaISA::VecOperandF64 = typedef VecOperand<VecElemF64, false> |
Definition at line 817 of file operand.hh.
using gem5::VegaISA::VecOperandI16 = typedef VecOperand<VecElemI16, false, 1> |
Definition at line 812 of file operand.hh.
using gem5::VegaISA::VecOperandI32 = typedef VecOperand<VecElemI32, false> |
Definition at line 814 of file operand.hh.
using gem5::VegaISA::VecOperandI64 = typedef VecOperand<VecElemI64, false> |
Definition at line 818 of file operand.hh.
using gem5::VegaISA::VecOperandI8 = typedef VecOperand<VecElemI8, false, 1> |
Definition at line 810 of file operand.hh.
using gem5::VegaISA::VecOperandU128 = typedef VecOperand<VecElemU32, false, 4> |
Definition at line 820 of file operand.hh.
using gem5::VegaISA::VecOperandU16 = typedef VecOperand<VecElemU16, false, 1> |
Definition at line 811 of file operand.hh.
using gem5::VegaISA::VecOperandU256 = typedef VecOperand<VecElemU32, false, 8> |
Definition at line 821 of file operand.hh.
using gem5::VegaISA::VecOperandU32 = typedef VecOperand<VecElemU32, false> |
Definition at line 813 of file operand.hh.
using gem5::VegaISA::VecOperandU512 = typedef VecOperand<VecElemU32, false, 16> |
Definition at line 822 of file operand.hh.
using gem5::VegaISA::VecOperandU64 = typedef VecOperand<VecElemU64, false> |
Definition at line 816 of file operand.hh.
using gem5::VegaISA::VecOperandU8 = typedef VecOperand<VecElemU8, false, 1> |
Definition at line 809 of file operand.hh.
using gem5::VegaISA::VecOperandU96 = typedef VecOperand<VecElemU32, false, 3> |
Definition at line 819 of file operand.hh.
using gem5::VegaISA::VecRegContainerU32 = typedef VecRegContainer<sizeof(VecElemU32) * NumVecElemPerVecReg> |
Definition at line 178 of file gpu_registers.hh.
using gem5::VegaISA::VecRegContainerU64 = typedef VecRegContainer<sizeof(VecElemU64) * NumVecElemPerVecReg> |
Definition at line 180 of file gpu_registers.hh.
enum gem5::VegaISA::ExceptionCode : uint64_t |
enum gem5::VegaISA::OpSelector : int |
Definition at line 48 of file gpu_registers.hh.
gem5::VegaISA::BitUnion64 | ( | PageTableEntry | ) |
The page table entry is reverse engineered from the macros here:
https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h#L53
uint16_t gem5::VegaISA::clampF16 | ( | uint16_t | value, |
bool | clamp | ||
) |
Definition at line 103 of file vop3p.cc.
References gem5::ArmISA::fplibMax(), gem5::ArmISA::fplibMin(), and gem5::ArmISA::imm.
Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_FMA_F16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_ADD_F16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MUL_F16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MIN_F16::execute(), and gem5::VegaISA::Inst_VOP3P__V_PK_MAX_F16::execute().
float gem5::VegaISA::clampF32 | ( | float | value, |
bool | clamp | ||
) |
Definition at line 120 of file vop3p.cc.
Referenced by gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute().
int16_t gem5::VegaISA::clampI16 | ( | int32_t | value, |
bool | clamp | ||
) |
Definition at line 79 of file vop3p.cc.
Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_MAD_I16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_ADD_I16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_SUB_I16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MAX_I16::execute(), and gem5::VegaISA::Inst_VOP3P__V_PK_MIN_I16::execute().
uint16_t gem5::VegaISA::clampU16 | ( | uint32_t | value, |
bool | clamp | ||
) |
Definition at line 91 of file vop3p.cc.
Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_MAD_U16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_ADD_U16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_SUB_U16::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MAX_U16::execute(), and gem5::VegaISA::Inst_VOP3P__V_PK_MIN_U16::execute().
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Definition at line 121 of file inst_util.hh.
References gem5::popCount(), and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32::execute(), and gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64::execute().
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Definition at line 164 of file inst_util.hh.
References gem5::findMsbSet(), and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32::execute(), and gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64::execute().
int32_t gem5::VegaISA::dotClampI | ( | int32_t | value, |
bool | clamp | ||
) |
uint32_t gem5::VegaISA::dotClampU | ( | uint32_t | value, |
bool | clamp | ||
) |
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dppInstImpl is a helper function that performs the inputted operation on the inputted vector register lane.
The returned output lane represents the input lane given the destination lane and DPP_CTRL word.
Currently the values are: 0x0 - 0xFF: full permute of four threads 0x100: reserved 0x101 - 0x10F: row shift left by 1-15 threads 0x111 - 0x11F: row shift right by 1-15 threads 0x121 - 0x12F: row rotate right by 1-15 threads 0x130: wavefront left shift by 1 thread 0x134: wavefront left rotate by 1 thread 0x138: wavefront right shift by 1 thread 0x13C: wavefront right rotate by 1 thread 0x140: mirror threads within row 0x141: mirror threads within 1/2 row (8 threads) 0x142: broadcast 15th thread of each row to next row 0x143: broadcast thread 31 to rows 2 and 3
Definition at line 320 of file inst_util.hh.
References gem5::X86ISA::count, gem5::ArmISA::NumVecElemPerVecReg, panic, gem5::ROW_SIZE, gem5::SQ_DPP_QUAD_PERM_MAX, gem5::SQ_DPP_RESERVED, gem5::SQ_DPP_ROW_BCAST15, gem5::SQ_DPP_ROW_BCAST31, gem5::SQ_DPP_ROW_HALF_MIRROR, gem5::SQ_DPP_ROW_MIRROR, gem5::SQ_DPP_ROW_RR1, gem5::SQ_DPP_ROW_RR15, gem5::SQ_DPP_ROW_SL1, gem5::SQ_DPP_ROW_SL15, gem5::SQ_DPP_ROW_SR1, gem5::SQ_DPP_ROW_SR15, gem5::SQ_DPP_WF_RL1, gem5::SQ_DPP_WF_RR1, gem5::SQ_DPP_WF_SL1, and gem5::SQ_DPP_WF_SR1.
Referenced by processDPP().
gem5::VegaISA::EndBitUnion | ( | PageTableEntry | ) |
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Definition at line 142 of file inst_util.hh.
References gem5::findLsbSet(), and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64::execute(), gem5::VegaISA::Inst_VOP1__V_FFBL_B32::execute(), and gem5::VegaISA::Inst_VOP3__V_FFBL_B32::execute().
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Definition at line 153 of file inst_util.hh.
References gem5::findMsbSet(), and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_VOP1__V_FFBH_U32::execute(), and gem5::VegaISA::Inst_VOP3__V_FFBH_U32::execute().
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Definition at line 131 of file inst_util.hh.
References gem5::findLsbSet(), and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32::execute(), and gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64::execute().
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Definition at line 174 of file inst_util.hh.
References gem5::X86ISA::count, gem5::ArmISA::i, and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_FLBIT_I32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64::execute(), gem5::VegaISA::Inst_VOP1__V_FFBH_I32::execute(), and gem5::VegaISA::Inst_VOP3__V_FFBH_I32::execute().
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Definition at line 210 of file inst_util.hh.
References gem5::X86ISA::count, gem5::ArmISA::i, and gem5::X86ISA::val.
bool gem5::VegaISA::isConstVal | ( | int | opIdx | ) |
Definition at line 209 of file gpu_registers.cc.
References isNegConstVal(), and isPosConstVal().
Referenced by gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::readSpecialVal().
bool gem5::VegaISA::isExecMask | ( | int | opIdx | ) |
Definition at line 222 of file gpu_registers.cc.
References REG_EXEC_HI, and REG_EXEC_LO.
Referenced by gem5::VegaISA::VEGAGPUStaticInst::isExecMaskRegister().
bool gem5::VegaISA::isFlatScratchReg | ( | int | opIdx | ) |
Definition at line 234 of file gpu_registers.cc.
References REG_FLAT_SCRATCH_HI, and REG_FLAT_SCRATCH_LO.
Referenced by gem5::VegaISA::VEGAGPUStaticInst::isFlatScratchRegister().
bool gem5::VegaISA::isLiteral | ( | int | opIdx | ) |
Definition at line 216 of file gpu_registers.cc.
References REG_SRC_LITERAL.
bool gem5::VegaISA::isNegConstVal | ( | int | opIdx | ) |
Definition at line 200 of file gpu_registers.cc.
References REG_INT_CONST_NEG_MAX, and REG_INT_CONST_NEG_MIN.
Referenced by isConstVal(), and gem5::VegaISA::GPUISA::readConstVal().
bool gem5::VegaISA::isPosConstVal | ( | int | opIdx | ) |
Definition at line 191 of file gpu_registers.cc.
References REG_INT_CONST_POS_MAX, and REG_INT_CONST_POS_MIN.
Referenced by isConstVal(), and gem5::VegaISA::GPUISA::readConstVal().
bool gem5::VegaISA::isScalarReg | ( | int | opIdx | ) |
Definition at line 240 of file gpu_registers.cc.
References REG_FLAT_SCRATCH_HI, REG_FLAT_SCRATCH_LO, REG_SGPR_MAX, REG_VCC_HI, and REG_VCC_LO.
Referenced by gem5::VegaISA::Inst_SOP2::initOperandInfo(), gem5::VegaISA::Inst_SOPK::initOperandInfo(), gem5::VegaISA::Inst_SOP1::initOperandInfo(), gem5::VegaISA::Inst_SOPC::initOperandInfo(), gem5::VegaISA::Inst_SMEM::initOperandInfo(), gem5::VegaISA::Inst_VOP2::initOperandInfo(), gem5::VegaISA::Inst_VOP1::initOperandInfo(), gem5::VegaISA::Inst_VOPC::initOperandInfo(), gem5::VegaISA::Inst_VOP3A::initOperandInfo(), gem5::VegaISA::Inst_VOP3B::initOperandInfo(), gem5::VegaISA::Inst_VOP3P::initOperandInfo(), gem5::VegaISA::Inst_VOP3P_MAI::initOperandInfo(), gem5::VegaISA::Inst_MUBUF::initOperandInfo(), gem5::VegaISA::Inst_MTBUF::initOperandInfo(), gem5::VegaISA::Inst_MIMG::initOperandInfo(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::read(), and gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::write().
bool gem5::VegaISA::isVccReg | ( | int | opIdx | ) |
Definition at line 228 of file gpu_registers.cc.
References REG_VCC_HI, and REG_VCC_LO.
bool gem5::VegaISA::isVectorReg | ( | int | opIdx | ) |
Definition at line 253 of file gpu_registers.cc.
References REG_VGPR_MAX, and REG_VGPR_MIN.
Referenced by gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA< _delta, M, N, K, B, T1, T2, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_MXFP< M, N, K, B, MXFPT, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP2::initOperandInfo(), gem5::VegaISA::Inst_VOP1::initOperandInfo(), gem5::VegaISA::Inst_VOPC::initOperandInfo(), gem5::VegaISA::Inst_VOP3A::initOperandInfo(), gem5::VegaISA::Inst_VOP3B::initOperandInfo(), gem5::VegaISA::Inst_VOP3P::initOperandInfo(), gem5::VegaISA::Inst_VOP3P_MAI::initOperandInfo(), and gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::readSrc().
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Definition at line 247 of file inst_util.hh.
Referenced by gem5::VegaISA::Inst_VOP3__V_MED3_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MED3_I32::execute(), and gem5::VegaISA::Inst_VOP3__V_MED3_U32::execute().
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Definition at line 286 of file inst_util.hh.
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Definition at line 272 of file inst_util.hh.
Referenced by gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32::execute(), and gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32::execute().
const int gem5::VegaISA::NumVecElemPerVecReg | ( | 64 | ) |
Referenced by gem5::initMemReqHelper(), gem5::initScratchReqHelper(), and gem5::GPUCommandProcessor::MQDDmaEvent().
int gem5::VegaISA::opSelectorToRegIdx | ( | int | idx, |
int | numScalarRegs | ||
) |
the VCC register occupies the two highest numbered SRF entries. VCC is typically indexed by specifying VCC_LO (simply called VCC) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the VCC register.
VCC_LO = s[NUM_SGPRS - 2] VCC_HI = s[NUM_SGPRS - 1]
the FLAT_SCRATCH register occupies the two SRF entries just below VCC. FLAT_SCRATCH is typically indexed by specifying FLAT_SCRATCH_LO (simply called FLAT_SCRATCH) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the FLAT_SCRATCH register.
FLAT_SCRATCH_LO = s[NUM_SGPRS - 4] FLAT_SCRATCH_HI = s[NUM_SGPRS - 3]
If the operand is the EXEC mask we just return the op selector value indicating it is the EXEC mask, which is not part of any RF. Higher-level calls will understand that this resolves to a special system register, not an index into an RF.
Definition at line 137 of file gpu_registers.cc.
References REG_EXEC_HI, REG_EXEC_LO, REG_FLAT_SCRATCH_HI, REG_FLAT_SCRATCH_LO, REG_SGPR_MAX, REG_VCC_HI, REG_VCC_LO, REG_VGPR_MAX, and REG_VGPR_MIN.
Referenced by gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::readSrc().
std::string gem5::VegaISA::opSelectorToRegSym | ( | int | idx, |
int | numRegs | ||
) |
Definition at line 40 of file gpu_registers.cc.
References fatal, REG_EXEC_LO, REG_FLAT_SCRATCH_HI, REG_FLAT_SCRATCH_LO, REG_INT_CONST_NEG_MAX, REG_INT_CONST_NEG_MIN, REG_INT_CONST_POS_MAX, REG_INT_CONST_POS_MIN, REG_M0, REG_NEG_FOUR, REG_NEG_HALF, REG_NEG_ONE, REG_NEG_TWO, REG_POS_FOUR, REG_POS_HALF, REG_POS_ONE, REG_POS_TWO, REG_PRIVATE_BASE, REG_PRIVATE_LIMIT, REG_SGPR_MAX, REG_SHARED_BASE, REG_SHARED_LIMIT, REG_VCC_HI, REG_VCC_LO, REG_VGPR_MAX, REG_VGPR_MIN, and REG_ZERO.
Referenced by gem5::VegaISA::Inst_SOP2::generateDisassembly(), gem5::VegaISA::Inst_SOPK::generateDisassembly(), gem5::VegaISA::Inst_SOP1::generateDisassembly(), gem5::VegaISA::Inst_SOPC::generateDisassembly(), gem5::VegaISA::Inst_VOP2::generateDisassembly(), gem5::VegaISA::Inst_VOP1::generateDisassembly(), gem5::VegaISA::Inst_VOPC::generateDisassembly(), gem5::VegaISA::Inst_VOP3A::generateDisassembly(), gem5::VegaISA::Inst_VOP3B::generateDisassembly(), gem5::VegaISA::Inst_VOP3P::generateDisassembly(), gem5::VegaISA::Inst_VOP3P_MAI::generateDisassembly(), gem5::VegaISA::Inst_FLAT::generateFlatDisassembly(), and gem5::VegaISA::Inst_FLAT::generateGlobalScratchDisassembly().
void gem5::VegaISA::processDPP | ( | GPUDynInstPtr | gpuDynInst, |
InFmt_VOP_DPP | dppInst, | ||
T & | src0 | ||
) |
processDPP is a helper function for implementing Data Parallel Primitive instructions.
This function may be called by many different VOP1 instructions to do operations within a register.
STEP 1a: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on src0 and/or src1.
NOTE: ABS takes priority over NEG.
STEP 2: check the row and bank mask values. These determine which threads are enabled for the subsequent DPP_CTRL operations.
STEP 4: Handle the potential values of DPP_CTRL: 0x0 - 0xFF: full permute of four threads 0x100: reserved 0x101 - 0x10F: row shift right by 1-15 threads 0x111 - 0x11F: row shift right by 1-15 threads 0x121 - 0x12F: row shift right by 1-15 threads 0x130: wavefront left shift by 1 thread 0x134: wavefront left rotate by 1 thread 0x138: wavefront right shift by 1 thread 0x13C: wavefront right rotate by 1 thread 0x140: mirror threads within row 0x141: mirror threads within 1/2 row (8 threads) 0x142: broadcast 15th thread of each row to next row 0x143: broadcast thread 31 to rows 2 and 3
STEP 4: Implement bound control for disabled threads. If thread is disabled but boundCtrl is set, then we need to set the source data to 0 (i.e., set this lane to 0).
Definition at line 424 of file inst_util.hh.
References gem5::VegaISA::InFmt_VOP_DPP::BANK_MASK, gem5::VegaISA::InFmt_VOP_DPP::BC, gem5::VegaISA::InFmt_VOP_DPP::DPP_CTRL, dppInstImpl(), gem5::NUM_BANKS, gem5::ArmISA::NumVecElemPerVecReg, gem5::VegaISA::InFmt_VOP_DPP::ROW_MASK, gem5::ROW_SIZE, gem5::VegaISA::InFmt_VOP_DPP::SRC0_ABS, and gem5::VegaISA::InFmt_VOP_DPP::SRC0_NEG.
Referenced by gem5::VegaISA::Inst_VOP2::dppHelper(), gem5::VegaISA::Inst_VOP2__V_ADD_F32::execute(), gem5::VegaISA::Inst_VOP2__V_AND_B32::execute(), gem5::VegaISA::Inst_VOP2__V_MAC_F32::execute(), gem5::VegaISA::Inst_VOP1__V_MOV_B32::execute(), and processDPP().
void gem5::VegaISA::processDPP | ( | GPUDynInstPtr | gpuDynInst, |
InFmt_VOP_DPP | dppInst, | ||
T & | src0, | ||
T & | src1 | ||
) |
processDPP is a helper function for implementing Data Parallel Primitive instructions.
This function may be called by many different VOP2/VOPC instructions to do operations within a register.
STEP 1b: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on src0 and/or src1.
NOTE: ABS takes priority over NEG.
Definition at line 537 of file inst_util.hh.
References processDPP(), gem5::VegaISA::InFmt_VOP_DPP::SRC1_ABS, and gem5::VegaISA::InFmt_VOP_DPP::SRC1_NEG.
void gem5::VegaISA::processSDWA_dst | ( | InFmt_VOP_SDWA | sdwaInst, |
T & | dst, | ||
T & | origDst | ||
) |
processSDWA_dst is a helper function for implementing sub d-word addressing instructions for the dst operand.
This function may be called by many different VOP1/VOP2/VOPC instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.
STEP 1: select the appropriate bits for dst and pad/sign-extend as appropriate.
Definition at line 892 of file inst_util.hh.
References gem5::VegaISA::InFmt_VOP_SDWA::CLMP, gem5::VegaISA::InFmt_VOP_SDWA::DST_SEL, gem5::VegaISA::InFmt_VOP_SDWA::DST_U, and sdwaInstDstImpl().
Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::VegaISA::Inst_VOP2::sdwaDstHelper().
void gem5::VegaISA::processSDWA_src | ( | InFmt_VOP_SDWA | sdwaInst, |
T & | src0, | ||
T & | origSrc0 | ||
) |
processSDWA_src is a helper function for implementing sub d-word addressing instructions for the src operands.
This function may be called by many different VOP1 instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.
Definition at line 836 of file inst_util.hh.
References processSDWA_src_helper(), gem5::VegaISA::InFmt_VOP_SDWA::SRC0_ABS, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_NEG, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEL, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEXT, gem5::VegaISA::InFmt_VOP_SDWA::SRC1_ABS, gem5::VegaISA::InFmt_VOP_SDWA::SRC1_NEG, and gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEXT.
Referenced by gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), and gem5::VegaISA::Inst_VOP2::sdwaSrcHelper().
void gem5::VegaISA::processSDWA_src | ( | InFmt_VOP_SDWA | sdwaInst, |
T & | src0, | ||
T & | origSrc0, | ||
T & | src1, | ||
T & | origSrc1 | ||
) |
processSDWA_src is a helper function for implementing sub d-word addressing instructions.
This function may be called by many different VOP2/VOPC instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.
Definition at line 864 of file inst_util.hh.
References processSDWA_src_helper(), gem5::VegaISA::InFmt_VOP_SDWA::SRC0_ABS, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_NEG, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEL, gem5::VegaISA::InFmt_VOP_SDWA::SRC0_SEXT, gem5::VegaISA::InFmt_VOP_SDWA::SRC1_ABS, gem5::VegaISA::InFmt_VOP_SDWA::SRC1_NEG, gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEL, and gem5::VegaISA::InFmt_VOP_SDWA::SRC1_SEXT.
void gem5::VegaISA::processSDWA_src_helper | ( | T & | currSrc, |
T & | origCurrSrc, | ||
const SDWASelVals | src_sel, | ||
const bool | src_signExt, | ||
const bool | src_abs, | ||
const bool | src_neg | ||
) |
processSDWA_srcHelper is a helper function for implementing sub d-word addressing instructions for the src operands.
This function may be called by many different VOP1/VOP2/VOPC instructions to do operations within a register. This function is also agnostic of which operand it is operating on, so that it can be called for any src operand.
STEP 1: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on the src operand.
NOTE: According to the CSim implementation, ABS takes priority over NEG.
STEP 2: select the appropriate bits for each lane of source operand.
Definition at line 801 of file inst_util.hh.
References sdwaInstSrcImpl().
Referenced by processSDWA_src(), and processSDWA_src().
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Definition at line 104 of file inst_util.hh.
References gem5::bits(), gem5::ArmISA::mask, and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32::execute(), and gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64::execute().
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Definition at line 259 of file inst_util.hh.
References gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_VOP1__V_RNDNE_F64::execute(), gem5::VegaISA::Inst_VOP1__V_RNDNE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_RNDNE_F64::execute(), and gem5::VegaISA::Inst_VOP3__V_RNDNE_F32::execute().
void gem5::VegaISA::sdwaInstDstImpl | ( | T & | dstOper, |
T & | origDstOper, | ||
const bool | clamp, | ||
const SDWASelVals | sel, | ||
const SDWADstVals | unusedBits_format | ||
) |
sdwaInstDestImpl is a helper function that selects the appropriate bits/bytes for the inputted dest operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value.
The desired behavior is:
Definition at line 780 of file inst_util.hh.
References gem5::ArmISA::NumVecElemPerVecReg, sdwaInstDstImpl_helper(), and gem5::ArmISA::sel.
Referenced by processSDWA_dst().
T gem5::VegaISA::sdwaInstDstImpl_helper | ( | T | currDstVal, |
const T | origDstVal, | ||
const bool | clamp, | ||
const SDWASelVals | sel, | ||
const SDWADstVals | unusedBits_format | ||
) |
sdwaInstDstImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending.
It returns the value after these operations are done on it.
Definition at line 679 of file inst_util.hh.
References gem5::bits(), BITS_PER_BYTE, BITS_PER_WORD, gem5::insertBits(), MSB_PER_BYTE, MSB_PER_WORD, panic, gem5::SDWA_DWORD, gem5::SDWA_UNUSED_PRESERVE, gem5::SDWA_UNUSED_SEXT, gem5::SDWA_WORD_0, and gem5::ArmISA::sel.
Referenced by sdwaInstDstImpl().
void gem5::VegaISA::sdwaInstSrcImpl | ( | T & | currOper, |
T & | origCurrOper, | ||
const SDWASelVals | sel, | ||
const bool | signExt | ||
) |
sdwaInstSrcImpl is a helper function that selects the appropriate bits/bytes for each lane of the inputted source operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value.
The desired behavior is:
Definition at line 660 of file inst_util.hh.
References gem5::ArmISA::NumVecElemPerVecReg, sdwaInstSrcImpl_helper(), and gem5::ArmISA::sel.
Referenced by processSDWA_src_helper().
T gem5::VegaISA::sdwaInstSrcImpl_helper | ( | T | currOperVal, |
const T | origOperVal, | ||
const SDWASelVals | sel, | ||
const bool | signExt | ||
) |
sdwaInstSrcImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending.
It returns the value after these operations are done on it.
Definition at line 567 of file inst_util.hh.
References gem5::bits(), BITS_PER_BYTE, BITS_PER_WORD, MSB_PER_BYTE, MSB_PER_WORD, panic, panic_if, gem5::SDWA_DWORD, gem5::SDWA_WORD_0, and gem5::ArmISA::sel.
Referenced by sdwaInstSrcImpl().
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Definition at line 90 of file inst_util.hh.
References gem5::bits(), gem5::ArmISA::mask, and gem5::X86ISA::val.
Referenced by gem5::VegaISA::Inst_SOP1__S_WQM_B32::execute(), and gem5::VegaISA::Inst_SOP1__S_WQM_B64::execute().
Bitfield<47, 6> gem5::VegaISA::baseAddr |
Definition at line 71 of file pagetable.hh.
const int gem5::VegaISA::BITS_PER_BYTE = 8 |
Definition at line 143 of file gpu_registers.hh.
Referenced by gem5::VegaISA::Inst_VOPC::sdwabSelect(), sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().
const int gem5::VegaISA::BITS_PER_WORD = 16 |
Definition at line 144 of file gpu_registers.hh.
Referenced by gem5::VegaISA::Inst_VOPC::sdwabSelect(), sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().
gem5::VegaISA::blockFragmentSize |
Definition at line 69 of file pagetable.hh.
Referenced by gem5::VegaISA::Walker::WalkerState::walkStateMachine().
Bitfield< 2 > gem5::VegaISA::c |
Definition at line 63 of file pagetable.hh.
const int gem5::VegaISA::DWordSize = sizeof(VecElemU32) |
Definition at line 172 of file gpu_registers.hh.
Bitfield<56> gem5::VegaISA::f |
Definition at line 53 of file pagetable.hh.
Bitfield<11, 7> gem5::VegaISA::fragment |
Definition at line 58 of file pagetable.hh.
Referenced by gem5::VegaISA::Walker::WalkerState::walkStateMachine().
Bitfield<55> gem5::VegaISA::l |
Definition at line 54 of file pagetable.hh.
gem5::VegaISA::m |
Definition at line 52 of file pagetable.hh.
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Definition at line 44604 of file instructions.hh.
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Definition at line 44375 of file instructions.hh.
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Definition at line 44610 of file instructions.hh.
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Definition at line 44369 of file instructions.hh.
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Definition at line 44356 of file instructions.hh.
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Definition at line 44363 of file instructions.hh.
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Definition at line 44616 of file instructions.hh.
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Definition at line 44634 of file instructions.hh.
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Definition at line 44350 of file instructions.hh.
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Definition at line 44628 of file instructions.hh.
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Definition at line 44388 of file instructions.hh.
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Definition at line 44382 of file instructions.hh.
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Definition at line 44852 of file instructions.hh.
const int gem5::VegaISA::MSB_PER_BYTE = (BITS_PER_BYTE - 1) |
Definition at line 145 of file gpu_registers.hh.
Referenced by sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().
const int gem5::VegaISA::MSB_PER_WORD = (BITS_PER_WORD - 1) |
Definition at line 146 of file gpu_registers.hh.
Referenced by gem5::VegaISA::Inst_VOPC::sdwabSelect(), sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().
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Definition at line 44622 of file instructions.hh.
const int gem5::VegaISA::NumNegConstRegs |
Definition at line 141 of file gpu_registers.hh.
const int gem5::VegaISA::NumPosConstRegs |
Definition at line 138 of file gpu_registers.hh.
Bitfield<54> gem5::VegaISA::p |
Definition at line 70 of file pagetable.hh.
Definition at line 42 of file page_size.hh.
Referenced by gem5::VegaTLBCoalescer::canCoalesce(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::VegaTLBCoalescer::processProbeTLBEvent(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaTLBCoalescer::CpuSidePort::recvFunctional(), gem5::VegaISA::GpuTLB::CpuSidePort::recvTimingReq(), gem5::VegaISA::GpuTLB::MemSidePort::recvTimingResp(), gem5::VegaTLBCoalescer::updatePhysAddresses(), and gem5::VegaISA::GpuTLB::walkerResponse().
const Addr gem5::VegaISA::PageShift = 12 |
Definition at line 41 of file page_size.hh.
Referenced by gem5::VegaISA::GpuTLB::demapPage(), gem5::VegaISA::Walker::WalkerState::initState(), gem5::VegaISA::GpuTLB::insert(), gem5::VegaISA::GpuTLB::lookup(), gem5::VegaISA::GpuTLB::lookupIt(), gem5::VegaISA::GpuTLB::pageAlign(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::WalkerState::startFunctional(), gem5::VegaISA::Walker::startTiming(), gem5::VegaISA::Walker::WalkerState::startWalk(), gem5::VegaISA::GpuTLB::walkerResponse(), and gem5::VegaISA::Walker::WalkerState::walkStateMachine().
Bitfield<47, 12> gem5::VegaISA::ppn |
Definition at line 57 of file pagetable.hh.
Bitfield<5> gem5::VegaISA::r |
Definition at line 60 of file pagetable.hh.
const int gem5::VegaISA::RegSizeDWords = sizeof(VecElemU32) / DWordSize |
Size of a single-precision register in DWords.
Definition at line 176 of file gpu_registers.hh.
Bitfield< 1 > gem5::VegaISA::s |
Definition at line 64 of file pagetable.hh.
Bitfield<53,52> gem5::VegaISA::sw |
Definition at line 55 of file pagetable.hh.
Bitfield<51> gem5::VegaISA::t |
Definition at line 56 of file pagetable.hh.
Bitfield< 0 > gem5::VegaISA::v |
Definition at line 65 of file pagetable.hh.
Bitfield<6> gem5::VegaISA::w |
Definition at line 59 of file pagetable.hh.
Bitfield<4> gem5::VegaISA::x |
Definition at line 61 of file pagetable.hh.
Bitfield<3> gem5::VegaISA::z |
Definition at line 62 of file pagetable.hh.