gem5  v22.1.0.0
se_workload.cc
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27 
28 #include "arch/mips/se_workload.hh"
29 
30 namespace gem5
31 {
32 
33 namespace MipsISA
34 {
35 
39 };
40 
41 } // namespace MipsISA
42 } // namespace gem5
STL vector class.
Definition: stl.hh:37
constexpr RegId A1
Definition: int.hh:141
constexpr RegId T1
Definition: int.hh:147
constexpr RegId A0
Definition: int.hh:140
constexpr RegId T0
Definition: int.hh:146
constexpr RegId A2
Definition: int.hh:142
constexpr RegId A3
Definition: int.hh:143
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
static const std::vector< RegId > ArgumentRegs
Definition: se_workload.hh:65

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