gem5  v21.1.0.2
int.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
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28  */
29 
30 #ifndef __ARCH_MIPS_REGS_INT_HH__
31 #define __ARCH_MIPS_REGS_INT_HH__
32 
33 namespace gem5
34 {
35 
36 namespace MipsISA
37 {
38 
39 // Constants Related to the number of registers
40 const int NumIntArchRegs = 32;
41 const int NumIntSpecialRegs = 9;
42 
43 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
44 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
45 
47 {
63 };
64 
65 // semantically meaningful register indices
66 const int SyscallSuccessReg = 7;
67 const int FirstArgumentReg = 4;
68 const int ReturnValueReg = 2;
69 
70 const int StackPointerReg = 29;
71 
72 const int SyscallPseudoReturnReg = 3;
73 
74 } // namespace MipsISA
75 } // namespace gem5
76 
77 #endif
gem5::MipsISA::NumIntArchRegs
const int NumIntArchRegs
Definition: int.hh:40
gem5::MipsISA::INTREG_DSP_ACX3
@ INTREG_DSP_ACX3
Definition: int.hh:61
gem5::MipsISA::MiscIntRegNums
MiscIntRegNums
Definition: int.hh:46
gem5::MipsISA::INTREG_DSP_HI2
@ INTREG_DSP_HI2
Definition: int.hh:57
gem5::MipsISA::INTREG_DSP_LO1
@ INTREG_DSP_LO1
Definition: int.hh:53
gem5::MipsISA::INTREG_DSP_LO0
@ INTREG_DSP_LO0
Definition: int.hh:49
gem5::MipsISA::SyscallPseudoReturnReg
const int SyscallPseudoReturnReg
Definition: int.hh:72
gem5::MipsISA::MaxShadowRegSets
const int MaxShadowRegSets
Definition: int.hh:43
gem5::MipsISA::INTREG_DSP_HI1
@ INTREG_DSP_HI1
Definition: int.hh:54
gem5::MipsISA::INTREG_DSP_ACX1
@ INTREG_DSP_ACX1
Definition: int.hh:55
gem5::MipsISA::INTREG_DSP_ACX2
@ INTREG_DSP_ACX2
Definition: int.hh:58
gem5::MipsISA::INTREG_DSP_ACX0
@ INTREG_DSP_ACX0
Definition: int.hh:52
gem5::MipsISA::ReturnValueReg
const int ReturnValueReg
Definition: int.hh:68
gem5::MipsISA::INTREG_DSP_CONTROL
@ INTREG_DSP_CONTROL
Definition: int.hh:62
gem5::MipsISA::NumIntSpecialRegs
const int NumIntSpecialRegs
Definition: int.hh:41
gem5::MipsISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:44
gem5::MipsISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:70
gem5::MipsISA::SyscallSuccessReg
const int SyscallSuccessReg
Definition: int.hh:66
gem5::MipsISA::FirstArgumentReg
const int FirstArgumentReg
Definition: int.hh:67
gem5::MipsISA::INTREG_LO
@ INTREG_LO
Definition: int.hh:48
gem5::MipsISA::INTREG_DSP_LO2
@ INTREG_DSP_LO2
Definition: int.hh:56
gem5::MipsISA::INTREG_DSP_HI3
@ INTREG_DSP_HI3
Definition: int.hh:60
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::INTREG_HI
@ INTREG_HI
Definition: int.hh:50
gem5::MipsISA::INTREG_DSP_HI0
@ INTREG_DSP_HI0
Definition: int.hh:51
gem5::MipsISA::INTREG_DSP_LO3
@ INTREG_DSP_LO3
Definition: int.hh:59

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