gem5 v24.0.0.0
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Enumerations | Variables
gem5::MipsISA::int_reg Namespace Reference

Enumerations

enum  : RegIndex {
  _ZeroIdx = 0 , _AtIdx = 1 , _V0Idx = 2 , _V1Idx = 3 ,
  _A0Idx = 4 , _A1Idx = 5 , _A2Idx = 6 , _A3Idx = 7 ,
  _T0Idx = 8 , _T1Idx = 9 , _T2Idx = 10 , _T3Idx = 11 ,
  _T4Idx = 12 , _T5Idx = 13 , _T6Idx = 14 , _T7Idx = 15 ,
  _S0Idx = 16 , _S1Idx = 17 , _S2Idx = 18 , _S3Idx = 19 ,
  _S4Idx = 20 , _S5Idx = 21 , _S6Idx = 22 , _S7Idx = 23 ,
  _T8Idx = 24 , _T9Idx = 25 , _K0Idx = 26 , _K1Idx = 27 ,
  _GpIdx = 28 , _SpIdx = 29 , _S8Idx = 30 , _FpIdx = _S8Idx ,
  _RaIdx = 31 , NumArchRegs , _LoIdx = NumArchRegs , _DspLo0Idx = _LoIdx ,
  _HiIdx , _DspHi0Idx = _HiIdx , _DspAcx0Idx , _DspLo1Idx ,
  _DspHi1Idx , _DspAcx1Idx , _DspLo2Idx , _DspHi2Idx ,
  _DspAcx2Idx , _DspLo3Idx , _DspHi3Idx , _DspAcx3Idx ,
  _DspControlIdx , NumRegs
}
 

Variables

constexpr RegId Zero = intRegClass[_ZeroIdx]
 
constexpr RegId At = intRegClass[_AtIdx]
 
constexpr RegId V0 = intRegClass[_V0Idx]
 
constexpr RegId V1 = intRegClass[_V1Idx]
 
constexpr RegId A0 = intRegClass[_A0Idx]
 
constexpr RegId A1 = intRegClass[_A1Idx]
 
constexpr RegId A2 = intRegClass[_A2Idx]
 
constexpr RegId A3 = intRegClass[_A3Idx]
 
constexpr RegId T0 = intRegClass[_T0Idx]
 
constexpr RegId T1 = intRegClass[_T1Idx]
 
constexpr RegId T2 = intRegClass[_T2Idx]
 
constexpr RegId T3 = intRegClass[_T3Idx]
 
constexpr RegId T4 = intRegClass[_T4Idx]
 
constexpr RegId T5 = intRegClass[_T5Idx]
 
constexpr RegId T6 = intRegClass[_T6Idx]
 
constexpr RegId T7 = intRegClass[_T7Idx]
 
constexpr RegId T8 = intRegClass[_T8Idx]
 
constexpr RegId T9 = intRegClass[_T9Idx]
 
constexpr RegId S0 = intRegClass[_S0Idx]
 
constexpr RegId S1 = intRegClass[_S1Idx]
 
constexpr RegId S2 = intRegClass[_S2Idx]
 
constexpr RegId S3 = intRegClass[_S3Idx]
 
constexpr RegId S4 = intRegClass[_S4Idx]
 
constexpr RegId S5 = intRegClass[_S5Idx]
 
constexpr RegId S6 = intRegClass[_S6Idx]
 
constexpr RegId S7 = intRegClass[_S7Idx]
 
constexpr RegId K0 = intRegClass[_K0Idx]
 
constexpr RegId K1 = intRegClass[_K1Idx]
 
constexpr RegId Gp = intRegClass[_GpIdx]
 
constexpr RegId Sp = intRegClass[_SpIdx]
 
constexpr RegId Fp = intRegClass[_FpIdx]
 
constexpr RegId Ra = intRegClass[_RaIdx]
 
constexpr RegId DspLo0 = intRegClass[_DspLo0Idx]
 
constexpr RegId DspHi0 = intRegClass[_DspHi0Idx]
 
constexpr RegId DspAcx0 = intRegClass[_DspAcx0Idx]
 
constexpr RegId DspLo1 = intRegClass[_DspLo1Idx]
 
constexpr RegId DspHi1 = intRegClass[_DspHi1Idx]
 
constexpr RegId DspAcx1 = intRegClass[_DspAcx1Idx]
 
constexpr RegId DspLo2 = intRegClass[_DspLo2Idx]
 
constexpr RegId DspHi2 = intRegClass[_DspHi2Idx]
 
constexpr RegId DspAcx2 = intRegClass[_DspAcx2Idx]
 
constexpr RegId DspLo3 = intRegClass[_DspLo3Idx]
 
constexpr RegId DspHi3 = intRegClass[_DspHi3Idx]
 
constexpr RegId DspAcx3 = intRegClass[_DspAcx3Idx]
 
constexpr RegId DspControl = intRegClass[_DspControlIdx]
 
constexpr auto & S8 = Fp
 
constexpr auto & Lo = DspLo0
 
constexpr auto & Hi = DspHi0
 
constexpr auto & SyscallSuccess = A3
 

Enumeration Type Documentation

◆ anonymous enum

anonymous enum : RegIndex
Enumerator
_ZeroIdx 
_AtIdx 
_V0Idx 
_V1Idx 
_A0Idx 
_A1Idx 
_A2Idx 
_A3Idx 
_T0Idx 
_T1Idx 
_T2Idx 
_T3Idx 
_T4Idx 
_T5Idx 
_T6Idx 
_T7Idx 
_S0Idx 
_S1Idx 
_S2Idx 
_S3Idx 
_S4Idx 
_S5Idx 
_S6Idx 
_S7Idx 
_T8Idx 
_T9Idx 
_K0Idx 
_K1Idx 
_GpIdx 
_SpIdx 
_S8Idx 
_FpIdx 
_RaIdx 
NumArchRegs 
_LoIdx 
_DspLo0Idx 
_HiIdx 
_DspHi0Idx 
_DspAcx0Idx 
_DspLo1Idx 
_DspHi1Idx 
_DspAcx1Idx 
_DspLo2Idx 
_DspHi2Idx 
_DspAcx2Idx 
_DspLo3Idx 
_DspHi3Idx 
_DspAcx3Idx 
_DspControlIdx 
NumRegs 

Definition at line 48 of file int.hh.

Variable Documentation

◆ A0

RegId gem5::MipsISA::int_reg::A0 = intRegClass[_A0Idx]

Definition at line 140 of file int.hh.

Referenced by gem5::MipsProcess::argsInit().

◆ A1

RegId gem5::MipsISA::int_reg::A1 = intRegClass[_A1Idx]

Definition at line 141 of file int.hh.

Referenced by gem5::MipsProcess::argsInit().

◆ A2

RegId gem5::MipsISA::int_reg::A2 = intRegClass[_A2Idx]

Definition at line 142 of file int.hh.

◆ A3

RegId gem5::MipsISA::int_reg::A3 = intRegClass[_A3Idx]

Definition at line 143 of file int.hh.

◆ At

RegId gem5::MipsISA::int_reg::At = intRegClass[_AtIdx]

Definition at line 133 of file int.hh.

◆ DspAcx0

RegId gem5::MipsISA::int_reg::DspAcx0 = intRegClass[_DspAcx0Idx]

Definition at line 185 of file int.hh.

◆ DspAcx1

RegId gem5::MipsISA::int_reg::DspAcx1 = intRegClass[_DspAcx1Idx]

Definition at line 189 of file int.hh.

◆ DspAcx2

RegId gem5::MipsISA::int_reg::DspAcx2 = intRegClass[_DspAcx2Idx]

Definition at line 193 of file int.hh.

◆ DspAcx3

RegId gem5::MipsISA::int_reg::DspAcx3 = intRegClass[_DspAcx3Idx]

Definition at line 197 of file int.hh.

◆ DspControl

RegId gem5::MipsISA::int_reg::DspControl = intRegClass[_DspControlIdx]

Definition at line 199 of file int.hh.

◆ DspHi0

RegId gem5::MipsISA::int_reg::DspHi0 = intRegClass[_DspHi0Idx]

Definition at line 184 of file int.hh.

◆ DspHi1

RegId gem5::MipsISA::int_reg::DspHi1 = intRegClass[_DspHi1Idx]

Definition at line 188 of file int.hh.

◆ DspHi2

RegId gem5::MipsISA::int_reg::DspHi2 = intRegClass[_DspHi2Idx]

Definition at line 192 of file int.hh.

◆ DspHi3

RegId gem5::MipsISA::int_reg::DspHi3 = intRegClass[_DspHi3Idx]

Definition at line 196 of file int.hh.

◆ DspLo0

RegId gem5::MipsISA::int_reg::DspLo0 = intRegClass[_DspLo0Idx]

Definition at line 183 of file int.hh.

◆ DspLo1

RegId gem5::MipsISA::int_reg::DspLo1 = intRegClass[_DspLo1Idx]

Definition at line 187 of file int.hh.

◆ DspLo2

RegId gem5::MipsISA::int_reg::DspLo2 = intRegClass[_DspLo2Idx]

Definition at line 191 of file int.hh.

◆ DspLo3

RegId gem5::MipsISA::int_reg::DspLo3 = intRegClass[_DspLo3Idx]

Definition at line 195 of file int.hh.

◆ Fp

RegId gem5::MipsISA::int_reg::Fp = intRegClass[_FpIdx]

Definition at line 178 of file int.hh.

◆ Gp

RegId gem5::MipsISA::int_reg::Gp = intRegClass[_GpIdx]

Definition at line 172 of file int.hh.

◆ Hi

auto & gem5::MipsISA::int_reg::Hi = DspHi0

Definition at line 206 of file int.hh.

◆ K0

RegId gem5::MipsISA::int_reg::K0 = intRegClass[_K0Idx]

Definition at line 168 of file int.hh.

◆ K1

RegId gem5::MipsISA::int_reg::K1 = intRegClass[_K1Idx]

Definition at line 169 of file int.hh.

◆ Lo

auto & gem5::MipsISA::int_reg::Lo = DspLo0

Definition at line 205 of file int.hh.

◆ Ra

RegId gem5::MipsISA::int_reg::Ra = intRegClass[_RaIdx]

Definition at line 181 of file int.hh.

◆ S0

RegId gem5::MipsISA::int_reg::S0 = intRegClass[_S0Idx]

Definition at line 158 of file int.hh.

◆ S1

RegId gem5::MipsISA::int_reg::S1 = intRegClass[_S1Idx]

Definition at line 159 of file int.hh.

◆ S2

RegId gem5::MipsISA::int_reg::S2 = intRegClass[_S2Idx]

Definition at line 160 of file int.hh.

◆ S3

RegId gem5::MipsISA::int_reg::S3 = intRegClass[_S3Idx]

Definition at line 161 of file int.hh.

◆ S4

RegId gem5::MipsISA::int_reg::S4 = intRegClass[_S4Idx]

Definition at line 162 of file int.hh.

◆ S5

RegId gem5::MipsISA::int_reg::S5 = intRegClass[_S5Idx]

Definition at line 163 of file int.hh.

◆ S6

RegId gem5::MipsISA::int_reg::S6 = intRegClass[_S6Idx]

Definition at line 164 of file int.hh.

◆ S7

RegId gem5::MipsISA::int_reg::S7 = intRegClass[_S7Idx]

Definition at line 165 of file int.hh.

◆ S8

auto& gem5::MipsISA::int_reg::S8 = Fp
inlineconstexpr

Definition at line 203 of file int.hh.

◆ Sp

RegId gem5::MipsISA::int_reg::Sp = intRegClass[_SpIdx]

Definition at line 175 of file int.hh.

◆ SyscallSuccess

auto & gem5::MipsISA::int_reg::SyscallSuccess = A3

Definition at line 208 of file int.hh.

Referenced by gem5::guest_abi::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store().

◆ T0

RegId gem5::MipsISA::int_reg::T0 = intRegClass[_T0Idx]

Definition at line 146 of file int.hh.

◆ T1

RegId gem5::MipsISA::int_reg::T1 = intRegClass[_T1Idx]

Definition at line 147 of file int.hh.

◆ T2

RegId gem5::MipsISA::int_reg::T2 = intRegClass[_T2Idx]

Definition at line 148 of file int.hh.

◆ T3

RegId gem5::MipsISA::int_reg::T3 = intRegClass[_T3Idx]

Definition at line 149 of file int.hh.

◆ T4

RegId gem5::MipsISA::int_reg::T4 = intRegClass[_T4Idx]

Definition at line 150 of file int.hh.

◆ T5

RegId gem5::MipsISA::int_reg::T5 = intRegClass[_T5Idx]

Definition at line 151 of file int.hh.

◆ T6

RegId gem5::MipsISA::int_reg::T6 = intRegClass[_T6Idx]

Definition at line 152 of file int.hh.

◆ T7

RegId gem5::MipsISA::int_reg::T7 = intRegClass[_T7Idx]

Definition at line 153 of file int.hh.

◆ T8

RegId gem5::MipsISA::int_reg::T8 = intRegClass[_T8Idx]

Definition at line 154 of file int.hh.

◆ T9

RegId gem5::MipsISA::int_reg::T9 = intRegClass[_T9Idx]

Definition at line 155 of file int.hh.

◆ V0

RegId gem5::MipsISA::int_reg::V0 = intRegClass[_V0Idx]

Definition at line 136 of file int.hh.

Referenced by gem5::guest_abi::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store(), and gem5::MipsISA::EmuLinux::syscall().

◆ V1

RegId gem5::MipsISA::int_reg::V1 = intRegClass[_V1Idx]

Definition at line 137 of file int.hh.

Referenced by gem5::guest_abi::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store().

◆ Zero

RegId gem5::MipsISA::int_reg::Zero = intRegClass[_ZeroIdx]
inlineconstexpr

Definition at line 130 of file int.hh.

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