gem5
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arch
riscv
linux
se_workload.hh
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/*
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* Copyright 2004 The Regents of The University of Michigan
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* Copyright 2016 The University of Virginia
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_LINUX_SE_WORKLOAD_HH__
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#define __ARCH_RISCV_LINUX_SE_WORKLOAD_HH__
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#include "
arch/riscv/linux/linux.hh
"
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#include "
arch/riscv/page_size.hh
"
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#include "
arch/riscv/se_workload.hh
"
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#include "params/RiscvEmuLinux.hh"
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#include "
sim/syscall_desc.hh
"
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namespace
gem5
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{
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namespace
RiscvISA
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{
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class
EmuLinux
:
public
SEWorkload
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{
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protected
:
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static
SyscallDescTable<SEWorkload::SyscallABI64>
syscallDescs64
;
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static
SyscallDescTable<SEWorkload::SyscallABI32>
syscallDescs32
;
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public
:
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using
Params
= RiscvEmuLinuxParams;
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EmuLinux
(
const
Params
&
p
) :
SEWorkload
(
p
,
PageShift
) {}
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ByteOrder
byteOrder
()
const override
{
return
ByteOrder::little; }
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void
syscall
(
ThreadContext
*tc)
override
;
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};
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}
// namespace RiscvISA
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}
// namespace gem5
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#endif
// __ARCH_RISCV_LINUX_SE_WORKLOAD_HH__
linux.hh
se_workload.hh
gem5::RiscvISA::EmuLinux
Definition
se_workload.hh:46
gem5::RiscvISA::EmuLinux::syscallDescs32
static SyscallDescTable< SEWorkload::SyscallABI32 > syscallDescs32
32 bit syscall descriptors, indexed by call number.
Definition
se_workload.hh:53
gem5::RiscvISA::EmuLinux::syscall
void syscall(ThreadContext *tc) override
Definition
se_workload.cc:82
gem5::RiscvISA::EmuLinux::EmuLinux
EmuLinux(const Params &p)
Definition
se_workload.hh:58
gem5::RiscvISA::EmuLinux::syscallDescs64
static SyscallDescTable< SEWorkload::SyscallABI64 > syscallDescs64
64 bit syscall descriptors, indexed by call number.
Definition
se_workload.hh:50
gem5::RiscvISA::EmuLinux::byteOrder
ByteOrder byteOrder() const override
Definition
se_workload.hh:60
gem5::RiscvISA::EmuLinux::Params
RiscvEmuLinuxParams Params
Definition
se_workload.hh:56
gem5::RiscvISA::SEWorkload
Definition
se_workload.hh:45
gem5::SyscallDescTable
Definition
syscall_desc.hh:190
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::RiscvISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5::RiscvISA::PageShift
const Addr PageShift
Definition
page_size.hh:53
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
page_size.hh
syscall_desc.hh
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