se_workload.hh

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#ifndef __ARCH_RISCV_SE_WORKLOAD_HH__
#define __ARCH_RISCV_SE_WORKLOAD_HH__
 
#include "arch/riscv/reg_abi.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/remote_gdb.hh"
#include "params/RiscvSEWorkload.hh"
#include "sim/se_workload.hh"
#include "sim/syscall_abi.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
class SEWorkload : public gem5::SEWorkload
{
  public:
    PARAMS(RiscvSEWorkload);
 
    SEWorkload(const Params &p, Addr page_shift) :
        gem5::SEWorkload(p, page_shift)
    {}
 
    void
    setSystem(System *sys) override
    {
        gem5::SEWorkload::setSystem(sys);
        gdb = BaseRemoteGDB::build<RemoteGDB>(
                params().remote_gdb_port, system);
    }
 
    loader::Arch getArch() const override { return loader::Riscv64; }
 
    //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
    using SyscallABI = RegABI64;
};
 
} // namespace RiscvISA
 
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
namespace guest_abi
{
 
template <>
struct Result<RiscvISA::SEWorkload::SyscallABI, SyscallReturn>
{
    static void
    store(ThreadContext *tc, const SyscallReturn &ret)
    {
        if (ret.successful()) {
            // no error
            tc->setReg(RiscvISA::ReturnValueReg, ret.returnValue());
        } else {
            // got an error, return details
            tc->setReg(RiscvISA::ReturnValueReg, ret.encodedValue());
        }
    }
};
 
} // namespace guest_abi
} // namespace gem5
 
#endif // __ARCH_RISCV_SE_WORKLOAD_HH__