gem5  v21.1.0.2
pra_constants.hh
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28 
29 #ifndef __ARCH_RISCV_PRA_CONSTANTS_HH__
30 #define __ARCH_RISCV_PRA_CONSTANTS_HH__
31 
32 #include "arch/riscv/types.hh"
33 #include "base/bitunion.hh"
34 
35 namespace gem5
36 {
37 
38 namespace RiscvISA
39 {
40 
41 BitUnion32(IndexReg)
42  Bitfield<31> p;
43  // Need to figure out how to put in the TLB specific bits here
44  // For now, we assume that the entire length is used by the index
45  // field In reality, Index_HI = N-1, where
46  // N = Ceiling(log2(TLB Entries))
47  Bitfield<30, 0> index;
48 EndBitUnion(IndexReg)
49 
50 BitUnion32(RandomReg)
51  // This has a problem similar to the IndexReg index field. We'll keep
52  // both consistent at 30 for now
53  Bitfield<30, 0> random;
54 EndBitUnion(RandomReg)
55 
56 BitUnion64(EntryLoReg)
57  Bitfield<63, 30> fill;
58  Bitfield<29, 6> pfn; // Page frame number
59  Bitfield<5, 3> c; // Coherency attribute
60  Bitfield<2> d; // Dirty Bit
61  Bitfield<1> v; // Valid Bit
62  Bitfield<0> g; // Global Bit
63 EndBitUnion(EntryLoReg)
64 
65 BitUnion64(ContextReg)
66  Bitfield<63, 23> pteBase;
67  Bitfield<22, 4> badVPN2;
68  // Bits 3-0 are 0
69 EndBitUnion(ContextReg)
70 
71 BitUnion32(PageMaskReg)
72  // Bits 31-29 are 0
73  Bitfield<28, 13> mask;
74  Bitfield<12, 11> maskx;
75  // Bits 10-0 are zero
76 EndBitUnion(PageMaskReg)
77 
78 BitUnion32(PageGrainReg)
79  Bitfield<31, 30> aseUp;
80  Bitfield<29> elpa;
81  Bitfield<28> esp;
82  // Bits 27-13 are zeros
83  Bitfield<12, 8> aseDn;
84  // Bits 7-0 are zeros
85 EndBitUnion(PageGrainReg)
86 
87 BitUnion32(WiredReg)
88  // See note on Index register above
89  Bitfield<30, 0> wired;
90 EndBitUnion(WiredReg)
91 
92 BitUnion32(HWREnaReg)
93  Bitfield<31, 30> impl;
94  Bitfield<3, 0> mask;
95 EndBitUnion(HWREnaReg)
96 
97 BitUnion64(EntryHiReg)
98  Bitfield<63, 62> r;
99  Bitfield<61, 40> fill;
100  Bitfield<39, 13> vpn2;
101  Bitfield<12, 11> vpn2x;
102  Bitfield<7, 0> asid;
103 EndBitUnion(EntryHiReg)
104 
105 BitUnion32(StatusReg)
106  SubBitUnion(cu, 31, 28)
107  Bitfield<31> cu3;
108  Bitfield<30> cu2;
109  Bitfield<29> cu1;
110  Bitfield<28> cu0;
111  EndSubBitUnion(cu)
112  Bitfield<27> rp;
113  Bitfield<26> fr;
114  Bitfield<25> re;
115  Bitfield<24> mx;
116  Bitfield<23> px;
117  Bitfield<22> bev;
118  Bitfield<21> ts;
119  Bitfield<20> sr;
120  Bitfield<19> nmi;
121  // Bit 18 is zero
122  Bitfield<17, 16> impl;
123  Bitfield<15, 10> ipl;
124  SubBitUnion(im, 15, 8)
125  Bitfield<15> im7;
126  Bitfield<14> im6;
127  Bitfield<13> im5;
128  Bitfield<12> im4;
129  Bitfield<11> im3;
130  Bitfield<10> im2;
131  Bitfield<9> im1;
132  Bitfield<8> im0;
133  EndSubBitUnion(im)
134  Bitfield<7> kx;
135  Bitfield<6> sx;
136  Bitfield<5> ux;
137  Bitfield<4, 3> ksu;
138  Bitfield<4> um;
139  Bitfield<3> r0;
140  Bitfield<2> erl;
141  Bitfield<1> exl;
142  Bitfield<0> ie;
143 EndBitUnion(StatusReg)
144 
145 BitUnion32(IntCtlReg)
146  Bitfield<31, 29> ipti;
147  Bitfield<28, 26> ippci;
148  // Bits 26-10 are zeros
149  Bitfield<9, 5> vs;
150  // Bits 4-0 are zeros
151 EndBitUnion(IntCtlReg)
152 
153 BitUnion32(SRSCtlReg)
154  // Bits 31-30 are zeros
155  Bitfield<29, 26> hss;
156  // Bits 25-22 are zeros
157  Bitfield<21, 18> eicss;
158  // Bits 17-16 are zeros
159  Bitfield<15, 12> ess;
160  // Bits 11-10 are zeros
161  Bitfield<9, 6> pss;
162  // Bits 5-4 are zeros
163  Bitfield<3, 0> css;
164 EndBitUnion(SRSCtlReg)
165 
166 BitUnion32(SRSMapReg)
167  Bitfield<31, 28> ssv7;
168  Bitfield<27, 24> ssv6;
169  Bitfield<23, 20> ssv5;
170  Bitfield<19, 16> ssv4;
171  Bitfield<15, 12> ssv3;
172  Bitfield<11, 8> ssv2;
173  Bitfield<7, 4> ssv1;
174  Bitfield<3, 0> ssv0;
175 EndBitUnion(SRSMapReg)
176 
177 BitUnion32(CauseReg)
178  Bitfield<31> bd;
179  Bitfield<30> ti;
180  Bitfield<29, 28> ce;
181  Bitfield<27> dc;
182  Bitfield<26> pci;
183  // Bits 25-24 are zeros
184  Bitfield<23> iv;
185  Bitfield<22> wp;
186  // Bits 21-16 are zeros
187  Bitfield<15, 10> ripl;
188  SubBitUnion(ip, 15, 8)
189  Bitfield<15> ip7;
190  Bitfield<14> ip6;
191  Bitfield<13> ip5;
192  Bitfield<12> ip4;
193  Bitfield<11> ip3;
194  Bitfield<10> ip2;
195  Bitfield<9> ip1;
196  Bitfield<8> ip0;
198  // Bit 7 is zero
199  Bitfield<6, 2> excCode;
200  // Bits 1-0 are zeros
201 EndBitUnion(CauseReg)
202 
203 BitUnion32(PRIdReg)
204  Bitfield<31, 24> coOp;
205  Bitfield<23, 16> coId;
206  Bitfield<15, 8> procId;
207  Bitfield<7, 0> rev;
208 EndBitUnion(PRIdReg)
209 
210 BitUnion32(EBaseReg)
211  // Bit 31 is one
212  // Bit 30 is zero
213  Bitfield<29, 12> exceptionBase;
214  // Bits 11-10 are zeros
215  Bitfield<9, 9> cpuNum;
216 EndBitUnion(EBaseReg)
217 
218 BitUnion32(ConfigReg)
219  Bitfield<31> m;
220  Bitfield<30, 28> k23;
221  Bitfield<27, 25> ku;
222  Bitfield<24, 16> impl;
223  Bitfield<15> be;
224  Bitfield<14, 13> at;
225  Bitfield<12, 10> ar;
226  Bitfield<9, 7> mt;
227  // Bits 6-4 are zeros
228  Bitfield<3> vi;
229  Bitfield<2, 0> k0;
230 EndBitUnion(ConfigReg)
231 
232 BitUnion32(Config1Reg)
233  Bitfield<31> m;
234  Bitfield<30, 25> mmuSize;
235  Bitfield<24, 22> is;
236  Bitfield<21, 19> il;
237  Bitfield<18, 16> ia;
238  Bitfield<15, 13> ds;
239  Bitfield<12, 10> dl;
240  Bitfield<9, 7> da;
241  Bitfield<6> c2;
242  Bitfield<5> md;
243  Bitfield<4> pc;
244  Bitfield<3> wr;
245  Bitfield<2> ca;
246  Bitfield<1> ep;
247  Bitfield<0> fp;
248 EndBitUnion(Config1Reg)
249 
250 BitUnion32(Config2Reg)
251  Bitfield<31> m;
252  Bitfield<30, 28> tu;
253  Bitfield<27, 24> ts;
254  Bitfield<23, 20> tl;
255  Bitfield<19, 16> ta;
256  Bitfield<15, 12> su;
257  Bitfield<11, 8> ss;
258  Bitfield<7, 4> sl;
259  Bitfield<3, 0> sa;
260 EndBitUnion(Config2Reg)
261 
262 BitUnion32(Config3Reg)
263  Bitfield<31> m;
264  // Bits 30-11 are zeros
265  Bitfield<10> dspp;
266  // Bits 9-8 are zeros
267  Bitfield<7> lpa;
268  Bitfield<6> veic;
269  Bitfield<5> vint;
270  Bitfield<4> sp;
271  // Bit 3 is zero
272  Bitfield<2> mt;
273  Bitfield<1> sm;
274  Bitfield<0> tl;
275 EndBitUnion(Config3Reg)
276 
277 BitUnion64(WatchLoReg)
278  Bitfield<63, 3> vaddr;
279  Bitfield<2> i;
280  Bitfield<1> r;
281  Bitfield<0> w;
282 EndBitUnion(WatchLoReg)
283 
284 BitUnion32(WatchHiReg)
285  Bitfield<31> m;
286  Bitfield<30> g;
287  // Bits 29-24 are zeros
288  Bitfield<23, 16> asid;
289  // Bits 15-12 are zeros
290  Bitfield<11, 3> mask;
291  Bitfield<2> i;
292  Bitfield<1> r;
293  Bitfield<0> w;
294 EndBitUnion(WatchHiReg)
295 
296 BitUnion32(PerfCntCtlReg)
297  Bitfield<31> m;
298  Bitfield<30> w;
299  // Bits 29-11 are zeros
300  Bitfield<10, 5> event;
301  Bitfield<4> ie;
302  Bitfield<3> u;
303  Bitfield<2> s;
304  Bitfield<1> k;
305  Bitfield<0> exl;
306 EndBitUnion(PerfCntCtlReg)
307 
308 BitUnion32(CacheErrReg)
309  Bitfield<31> er;
310  Bitfield<30> ec;
311  Bitfield<29> ed;
312  Bitfield<28> et;
313  Bitfield<27> es;
314  Bitfield<26> ee;
315  Bitfield<25> eb;
316  Bitfield<24, 22> impl;
317  Bitfield<22, 0> index;
318 EndBitUnion(CacheErrReg)
319 
320 BitUnion32(TagLoReg)
321  Bitfield<31, 8> pTagLo;
322  Bitfield<7, 6> pState;
323  Bitfield<5> l;
324  Bitfield<4, 3> impl;
325  // Bits 2-1 are zeros
326  Bitfield<0> p;
327 EndBitUnion(TagLoReg)
328 
329 } // namespace RiscvISA
330 } // namespace gem5
331 
332 #endif
gem5::RiscvISA::ssv3
Bitfield< 15, 12 > ssv3
Definition: pra_constants.hh:171
gem5::RiscvISA::ip6
Bitfield< 14 > ip6
Definition: pra_constants.hh:190
gem5::RiscvISA::ip1
Bitfield< 9 > ip1
Definition: pra_constants.hh:195
gem5::RiscvISA::fr
Bitfield< 26 > fr
Definition: pra_constants.hh:113
gem5::RiscvISA::ip3
Bitfield< 11 > ip3
Definition: pra_constants.hh:193
gem5::RiscvISA::pteBase
pteBase
Definition: pra_constants.hh:66
gem5::RiscvISA::dspp
Bitfield< 10 > dspp
Definition: pra_constants.hh:265
gem5::RiscvISA::re
Bitfield< 25 > re
Definition: pra_constants.hh:114
gem5::RiscvISA::aseUp
aseUp
Definition: pra_constants.hh:79
gem5::RiscvISA::ee
Bitfield< 26 > ee
Definition: pra_constants.hh:314
gem5::RiscvISA::im6
Bitfield< 14 > im6
Definition: pra_constants.hh:126
gem5::RiscvISA::ca
Bitfield< 2 > ca
Definition: pra_constants.hh:245
gem5::RiscvISA::nmi
Bitfield< 19 > nmi
Definition: pra_constants.hh:120
gem5::RiscvISA::pci
Bitfield< 26 > pci
Definition: pra_constants.hh:182
gem5::RiscvISA::im4
Bitfield< 12 > im4
Definition: pra_constants.hh:128
gem5::RiscvISA::eicss
Bitfield< 21, 18 > eicss
Definition: pra_constants.hh:157
gem5::RiscvISA::random
random
Definition: pra_constants.hh:53
gem5::RiscvISA::veic
Bitfield< 6 > veic
Definition: pra_constants.hh:268
gem5::RiscvISA::wr
Bitfield< 3 > wr
Definition: pra_constants.hh:244
gem5::RiscvISA::cpuNum
Bitfield< 9, 9 > cpuNum
Definition: pra_constants.hh:215
gem5::RiscvISA::badVPN2
Bitfield< 22, 4 > badVPN2
Definition: pra_constants.hh:67
gem5::RiscvISA::ip4
Bitfield< 12 > ip4
Definition: pra_constants.hh:192
gem5::RiscvISA::ip2
Bitfield< 10 > ip2
Definition: pra_constants.hh:194
gem5::RiscvISA::ssv4
Bitfield< 19, 16 > ssv4
Definition: pra_constants.hh:170
gem5::RiscvISA::erl
Bitfield< 2 > erl
Definition: pra_constants.hh:140
gem5::RiscvISA::sm
Bitfield< 1 > sm
Definition: pra_constants.hh:273
gem5::RiscvISA::ippci
Bitfield< 28, 26 > ippci
Definition: pra_constants.hh:147
gem5::RiscvISA::sa
Bitfield< 3, 0 > sa
Definition: pra_constants.hh:259
gem5::RiscvISA::ksu
Bitfield< 4, 3 > ksu
Definition: pra_constants.hh:137
gem5::RiscvISA::sx
Bitfield< 6 > sx
Definition: pra_constants.hh:135
gem5::RiscvISA::ts
Bitfield< 21 > ts
Definition: pra_constants.hh:118
gem5::RiscvISA::ripl
Bitfield< 15, 10 > ripl
Definition: pra_constants.hh:187
gem5::PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:79
gem5::RiscvISA::coOp
coOp
Definition: pra_constants.hh:204
gem5::RiscvISA::esp
Bitfield< 28 > esp
Definition: pra_constants.hh:81
gem5::RiscvISA::cu2
Bitfield< 30 > cu2
Definition: pra_constants.hh:108
gem5::RiscvISA::su
Bitfield< 15, 12 > su
Definition: pra_constants.hh:256
gem5::RiscvISA::vpn2
Bitfield< 39, 13 > vpn2
Definition: pra_constants.hh:100
gem5::RiscvISA::dc
Bitfield< 27 > dc
Definition: pra_constants.hh:181
gem5::RiscvISA::ip5
Bitfield< 13 > ip5
Definition: pra_constants.hh:191
gem5::RiscvISA::c
Bitfield< 5, 3 > c
Definition: pra_constants.hh:59
gem5::RiscvISA::maskx
Bitfield< 12, 11 > maskx
Definition: pra_constants.hh:74
gem5::RiscvISA::ssv5
Bitfield< 23, 20 > ssv5
Definition: pra_constants.hh:169
gem5::RiscvISA::be
Bitfield< 15 > be
Definition: pra_constants.hh:223
gem5::RiscvISA::tu
Bitfield< 30, 28 > tu
Definition: pra_constants.hh:252
gem5::RiscvISA::et
Bitfield< 28 > et
Definition: pra_constants.hh:312
gem5::RiscvISA::cu0
Bitfield< 28 > cu0
Definition: pra_constants.hh:110
gem5::RiscvISA::BitUnion32
BitUnion32(IndexReg) Bitfield< 31 > p
gem5::RiscvISA::ti
Bitfield< 30 > ti
Definition: pra_constants.hh:179
gem5::RiscvISA::procId
Bitfield< 15, 8 > procId
Definition: pra_constants.hh:206
gem5::RiscvISA::k0
Bitfield< 2, 0 > k0
Definition: pra_constants.hh:229
gem5::RiscvISA::k23
Bitfield< 30, 28 > k23
Definition: pra_constants.hh:220
gem5::RiscvISA::bev
Bitfield< 22 > bev
Definition: pra_constants.hh:117
gem5::RiscvISA::pTagLo
pTagLo
Definition: pra_constants.hh:321
gem5::RiscvISA::im2
Bitfield< 10 > im2
Definition: pra_constants.hh:130
gem5::RiscvISA::wired
wired
Definition: pra_constants.hh:89
gem5::RiscvISA::ess
Bitfield< 15, 12 > ess
Definition: pra_constants.hh:159
gem5::RiscvISA::ce
Bitfield< 29, 28 > ce
Definition: pra_constants.hh:180
gem5::RiscvISA::css
Bitfield< 3, 0 > css
Definition: pra_constants.hh:163
gem5::RiscvISA::es
Bitfield< 27 > es
Definition: pra_constants.hh:313
gem5::RiscvISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::RiscvISA::ta
Bitfield< 19, 16 > ta
Definition: pra_constants.hh:255
gem5::RiscvISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::RiscvISA::sr
Bitfield< 20 > sr
Definition: pra_constants.hh:119
gem5::RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:257
gem5::RiscvISA::im0
Bitfield< 8 > im0
Definition: pra_constants.hh:132
gem5::RiscvISA::sp
Bitfield< 4 > sp
Definition: pra_constants.hh:270
gem5::RiscvISA::sl
Bitfield< 7, 4 > sl
Definition: pra_constants.hh:258
gem5::RiscvISA::ec
Bitfield< 30 > ec
Definition: pra_constants.hh:310
gem5::RiscvISA::ie
Bitfield< 0 > ie
Definition: pra_constants.hh:142
gem5::RiscvISA::w
Bitfield< 2 > w
Definition: pagetable.hh:74
gem5::RiscvISA::il
Bitfield< 21, 19 > il
Definition: pra_constants.hh:236
gem5::RiscvISA::is
Bitfield< 24, 22 > is
Definition: pra_constants.hh:235
gem5::RiscvISA::v
Bitfield< 0 > v
Definition: pagetable.hh:76
gem5::RiscvISA::aseDn
Bitfield< 12, 8 > aseDn
Definition: pra_constants.hh:83
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::ia
Bitfield< 18, 16 > ia
Definition: pra_constants.hh:237
gem5::RiscvISA::vs
Bitfield< 9, 5 > vs
Definition: pra_constants.hh:149
gem5::RiscvISA::u
Bitfield< 4 > u
Definition: pagetable.hh:71
gem5::RiscvISA::at
Bitfield< 14, 13 > at
Definition: pra_constants.hh:224
gem5::RiscvISA::dl
Bitfield< 12, 10 > dl
Definition: pra_constants.hh:239
bitunion.hh
gem5::RiscvISA::mt
Bitfield< 9, 7 > mt
Definition: pra_constants.hh:226
types.hh
gem5::RiscvISA::im3
Bitfield< 11 > im3
Definition: pra_constants.hh:129
gem5::RiscvISA::wp
Bitfield< 22 > wp
Definition: pra_constants.hh:185
gem5::RiscvISA::ssv7
ssv7
Definition: pra_constants.hh:167
gem5::RiscvISA::EndSubBitUnion
EndSubBitUnion(cu) Bitfield< 27 > rp
gem5::RiscvISA::ku
Bitfield< 27, 25 > ku
Definition: pra_constants.hh:221
gem5::RiscvISA::da
Bitfield< 9, 7 > da
Definition: pra_constants.hh:240
gem5::RiscvISA::ip0
Bitfield< 8 > ip0
Definition: pra_constants.hh:196
gem5::RiscvISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:254
gem5::RiscvISA::eb
Bitfield< 25 > eb
Definition: pra_constants.hh:315
gem5::RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:75
gem5::RiscvISA::fp
Bitfield< 0 > fp
Definition: pra_constants.hh:247
gem5::RiscvISA::s
Bitfield< 2 > s
Definition: pra_constants.hh:303
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::RiscvISA::asid
Bitfield< 59, 44 > asid
Definition: pagetable.hh:47
gem5::RiscvISA::ssv1
Bitfield< 7, 4 > ssv1
Definition: pra_constants.hh:173
gem5::RiscvISA::rev
Bitfield< 7, 0 > rev
Definition: pra_constants.hh:207
gem5::igbreg::txd_op::ip
bool ip(TxDesc *d)
Definition: i8254xGBe_defs.hh:277
gem5::RiscvISA::ep
Bitfield< 1 > ep
Definition: pra_constants.hh:246
gem5::RiscvISA::r0
Bitfield< 3 > r0
Definition: pra_constants.hh:139
gem5::RiscvISA::g
Bitfield< 5 > g
Definition: pagetable.hh:70
gem5::RiscvISA::mx
Bitfield< 24 > mx
Definition: pra_constants.hh:115
gem5::RiscvISA::um
Bitfield< 4 > um
Definition: pra_constants.hh:138
gem5::RiscvISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::RiscvISA::hss
hss
Definition: pra_constants.hh:155
gem5::RiscvISA::vi
Bitfield< 3 > vi
Definition: pra_constants.hh:228
gem5::RiscvISA::excCode
Bitfield< 6, 2 > excCode
Definition: pra_constants.hh:199
gem5::RiscvISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:238
gem5::RiscvISA::im5
Bitfield< 13 > im5
Definition: pra_constants.hh:127
gem5::RiscvISA::pfn
Bitfield< 29, 6 > pfn
Definition: pra_constants.hh:58
gem5::RiscvISA::ipl
Bitfield< 15, 10 > ipl
Definition: pra_constants.hh:123
gem5::RiscvISA::ux
Bitfield< 5 > ux
Definition: pra_constants.hh:136
gem5::ArmISA::m
Bitfield< 0 > m
Definition: misc_types.hh:394
gem5::RiscvISA::ssv0
Bitfield< 3, 0 > ssv0
Definition: pra_constants.hh:174
gem5::RiscvISA::c2
Bitfield< 6 > c2
Definition: pra_constants.hh:241
gem5::RiscvISA::fill
fill
Definition: pra_constants.hh:57
gem5::RiscvISA::vpn2x
Bitfield< 12, 11 > vpn2x
Definition: pra_constants.hh:101
gem5::RiscvISA::exl
Bitfield< 1 > exl
Definition: pra_constants.hh:141
gem5::RiscvISA::ssv6
Bitfield< 27, 24 > ssv6
Definition: pra_constants.hh:168
gem5::RiscvISA::mmuSize
Bitfield< 30, 25 > mmuSize
Definition: pra_constants.hh:234
gem5::RiscvISA::d
Bitfield< 7 > d
Definition: pagetable.hh:68
gem5::RiscvISA::md
Bitfield< 5 > md
Definition: pra_constants.hh:242
gem5::RiscvISA::vint
Bitfield< 5 > vint
Definition: pra_constants.hh:269
gem5::RiscvISA::SubBitUnion
SubBitUnion(im, 15, 8) Bitfield< 15 > im7
gem5::RiscvISA::pss
Bitfield< 9, 6 > pss
Definition: pra_constants.hh:161
gem5::RiscvISA::ssv2
Bitfield< 11, 8 > ssv2
Definition: pra_constants.hh:172
gem5::RiscvISA::elpa
Bitfield< 29 > elpa
Definition: pra_constants.hh:80
gem5::RiscvISA::lpa
Bitfield< 7 > lpa
Definition: pra_constants.hh:267
gem5::RiscvISA::impl
impl
Definition: pra_constants.hh:93
gem5::RiscvISA::k
Bitfield< 1 > k
Definition: pra_constants.hh:304
gem5::RiscvISA::EndBitUnion
EndBitUnion(SATP) enum AddrXlateMode
Definition: pagetable.hh:49
gem5::RiscvISA::cu3
Bitfield< 31 > cu3
Definition: pra_constants.hh:106
gem5::RiscvISA::px
Bitfield< 23 > px
Definition: pra_constants.hh:116
gem5::RiscvISA::exceptionBase
exceptionBase
Definition: pra_constants.hh:213
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::pState
Bitfield< 7, 6 > pState
Definition: pra_constants.hh:322
gem5::RiscvISA::ed
Bitfield< 29 > ed
Definition: pra_constants.hh:311
gem5::RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::RiscvISA::BitUnion64
BitUnion64(SATP) Bitfield< 63
gem5::RiscvISA::ipti
ipti
Definition: pra_constants.hh:146
gem5::RiscvISA::iv
Bitfield< 23 > iv
Definition: pra_constants.hh:184
gem5::RiscvISA::coId
Bitfield< 23, 16 > coId
Definition: pra_constants.hh:205
gem5::RiscvISA::im1
Bitfield< 9 > im1
Definition: pra_constants.hh:131
gem5::RiscvISA::ar
Bitfield< 12, 10 > ar
Definition: pra_constants.hh:225
gem5::RiscvISA::cu1
Bitfield< 29 > cu1
Definition: pra_constants.hh:109

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