Go to the source code of this file.
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| namespace | gem5 |
| | Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
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| namespace | gem5::RiscvISA |
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| | gem5::RiscvISA::rv_type |
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| Bitfield< 61 > | gem5::RiscvISA::compressed |
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| Bitfield< 57, 41 > | gem5::RiscvISA::vl |
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| Bitfield< 40 > | gem5::RiscvISA::vill |
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| Bitfield< 1, 0 > | gem5::RiscvISA::quadRant |
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| Bitfield< 6, 2 > | gem5::RiscvISA::opcode5 |
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| Bitfield< 6, 0 > | gem5::RiscvISA::opcode |
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| Bitfield< 31, 0 > | gem5::RiscvISA::all |
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| Bitfield< 11, 7 > | gem5::RiscvISA::rd |
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| Bitfield< 14, 12 > | gem5::RiscvISA::funct3 |
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| Bitfield< 19, 15 > | gem5::RiscvISA::rs1 |
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| Bitfield< 24, 20 > | gem5::RiscvISA::rs2 |
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| Bitfield< 31, 25 > | gem5::RiscvISA::funct7 |
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| Bitfield< 30 > | gem5::RiscvISA::srType |
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| Bitfield< 24, 20 > | gem5::RiscvISA::shamt5 |
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| Bitfield< 25, 20 > | gem5::RiscvISA::shamt6 |
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| Bitfield< 31, 20 > | gem5::RiscvISA::imm12 |
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| Bitfield< 23, 20 > | gem5::RiscvISA::succ |
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| Bitfield< 27, 24 > | gem5::RiscvISA::pred |
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| Bitfield< 11, 7 > | gem5::RiscvISA::imm5 |
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| Bitfield< 31, 25 > | gem5::RiscvISA::imm7 |
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| Bitfield< 31, 12 > | gem5::RiscvISA::imm20 |
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| Bitfield< 7 > | gem5::RiscvISA::bimm12bit11 |
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| Bitfield< 11, 8 > | gem5::RiscvISA::bimm12bits4to1 |
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| Bitfield< 30, 25 > | gem5::RiscvISA::bimm12bits10to5 |
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| Bitfield< 31 > | gem5::RiscvISA::immsign |
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| Bitfield< 30, 21 > | gem5::RiscvISA::ujimmbits10to1 |
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| Bitfield< 20 > | gem5::RiscvISA::ujimmbit11 |
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| Bitfield< 19, 12 > | gem5::RiscvISA::ujimmbits19to12 |
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| Bitfield< 31, 20 > | gem5::RiscvISA::funct12 |
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| Bitfield< 19, 15 > | gem5::RiscvISA::csrimm |
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| Bitfield< 11, 7 > | gem5::RiscvISA::fd |
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| Bitfield< 19, 15 > | gem5::RiscvISA::fs1 |
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| Bitfield< 24, 20 > | gem5::RiscvISA::fs2 |
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| Bitfield< 31, 27 > | gem5::RiscvISA::fs3 |
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| Bitfield< 14, 12 > | gem5::RiscvISA::round_mode |
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| Bitfield< 24, 20 > | gem5::RiscvISA::conv_sgn |
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| Bitfield< 26, 25 > | gem5::RiscvISA::funct2 |
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| Bitfield< 31, 27 > | gem5::RiscvISA::amofunct |
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| Bitfield< 26 > | gem5::RiscvISA::aq |
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| Bitfield< 25 > | gem5::RiscvISA::rl |
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| Bitfield< 15, 13 > | gem5::RiscvISA::copcode |
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| Bitfield< 12 > | gem5::RiscvISA::cfunct1 |
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| Bitfield< 11, 10 > | gem5::RiscvISA::cfunct2high |
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| Bitfield< 6, 5 > | gem5::RiscvISA::cfunct2low |
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| Bitfield< 11, 7 > | gem5::RiscvISA::rc1 |
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| Bitfield< 6, 2 > | gem5::RiscvISA::rc2 |
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| Bitfield< 9, 7 > | gem5::RiscvISA::rp1 |
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| Bitfield< 4, 2 > | gem5::RiscvISA::rp2 |
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| Bitfield< 11, 7 > | gem5::RiscvISA::fc1 |
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| Bitfield< 6, 2 > | gem5::RiscvISA::fc2 |
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| Bitfield< 4, 2 > | gem5::RiscvISA::fp2 |
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| Bitfield< 12, 2 > | gem5::RiscvISA::cjumpimm |
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| Bitfield< 5, 3 > | gem5::RiscvISA::cjumpimm3to1 |
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| Bitfield< 11, 11 > | gem5::RiscvISA::cjumpimm4to4 |
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| Bitfield< 2, 2 > | gem5::RiscvISA::cjumpimm5to5 |
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| Bitfield< 7, 7 > | gem5::RiscvISA::cjumpimm6to6 |
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| Bitfield< 6, 6 > | gem5::RiscvISA::cjumpimm7to7 |
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| Bitfield< 10, 9 > | gem5::RiscvISA::cjumpimm9to8 |
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| Bitfield< 8, 8 > | gem5::RiscvISA::cjumpimm10to10 |
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| Bitfield< 12 > | gem5::RiscvISA::cjumpimmsign |
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| Bitfield< 12, 5 > | gem5::RiscvISA::cimm8 |
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| Bitfield< 12, 7 > | gem5::RiscvISA::cimm6 |
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| Bitfield< 6, 2 > | gem5::RiscvISA::cimm5 |
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| Bitfield< 12, 10 > | gem5::RiscvISA::cimm3 |
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| Bitfield< 6, 5 > | gem5::RiscvISA::cimm2 |
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| Bitfield< 12 > | gem5::RiscvISA::cimm1 |
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| Bitfield< 31, 25 > | gem5::RiscvISA::m5func |
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| Bitfield< 31, 26 > | gem5::RiscvISA::vfunct6 |
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| Bitfield< 31, 27 > | gem5::RiscvISA::vfunct5 |
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| Bitfield< 27, 25 > | gem5::RiscvISA::vfunct3 |
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| Bitfield< 26, 25 > | gem5::RiscvISA::vfunct2 |
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| Bitfield< 31, 29 > | gem5::RiscvISA::nf |
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| Bitfield< 28 > | gem5::RiscvISA::mew |
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| Bitfield< 27, 26 > | gem5::RiscvISA::mop |
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| Bitfield< 25 > | gem5::RiscvISA::vm |
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| Bitfield< 24, 20 > | gem5::RiscvISA::lumop |
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| Bitfield< 24, 20 > | gem5::RiscvISA::sumop |
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| Bitfield< 14, 12 > | gem5::RiscvISA::width |
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| Bitfield< 24, 20 > | gem5::RiscvISA::vs2 |
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| Bitfield< 19, 15 > | gem5::RiscvISA::vs1 |
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| Bitfield< 11, 7 > | gem5::RiscvISA::vd |
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| Bitfield< 11, 7 > | gem5::RiscvISA::vs3 |
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| Bitfield< 19, 15 > | gem5::RiscvISA::vecimm |
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| Bitfield< 17, 15 > | gem5::RiscvISA::simm3 |
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| Bitfield< 31 > | gem5::RiscvISA::bit31 |
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| Bitfield< 30 > | gem5::RiscvISA::bit30 |
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| Bitfield< 30, 20 > | gem5::RiscvISA::zimm_vsetvli |
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| Bitfield< 31, 30 > | gem5::RiscvISA::bit31_30 |
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| Bitfield< 29, 20 > | gem5::RiscvISA::zimm_vsetivli |
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| Bitfield< 19, 15 > | gem5::RiscvISA::uimm_vsetivli |
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| Bitfield< 31, 25 > | gem5::RiscvISA::bit31_25 |
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| constexpr unsigned | gem5::RiscvISA::MaxVecLenInBytes = MaxVecLenInBits >> 3 |
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