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gem5 v24.0.0.0
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This is the complete list of members for gem5::ArmISA::ArmSev, including all inherited members.
| aarch64FaultSources | gem5::ArmISA::ArmFault | static |
| abortDisable(ThreadContext *tc) override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| AccessFlagLL enum value | gem5::ArmISA::ArmFault | |
| AddressSizeLL enum value | gem5::ArmISA::ArmFault | |
| AlignmentFault enum value | gem5::ArmISA::ArmFault | |
| annotate(AnnotationIDs id, uint64_t val) | gem5::ArmISA::ArmFault | inlinevirtual |
| AnnotationIDs enum name | gem5::ArmISA::ArmFault | |
| AR enum value | gem5::ArmISA::ArmFault | |
| ArmFault(ExtMachInst mach_inst=0, uint32_t _iss=0) | gem5::ArmISA::ArmFault | inline |
| ArmFaultVals(ExtMachInst mach_inst=0, uint32_t _iss=0) | gem5::ArmISA::ArmFaultVals< ArmSev > | inline |
| armPcElrOffset() override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| armPcOffset(bool is_hyp) override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| ArmSev() | gem5::ArmISA::ArmSev | inline |
| AsynchPtyErrOnMemoryAccess enum value | gem5::ArmISA::ArmFault | |
| AsynchronousExternalAbort enum value | gem5::ArmISA::ArmFault | |
| BRKPOINT enum value | gem5::ArmISA::ArmFault | |
| bStep | gem5::ArmISA::ArmFault | protected |
| CM enum value | gem5::ArmISA::ArmFault | |
| DebugEvent enum value | gem5::ArmISA::ArmFault | |
| DebugType enum name | gem5::ArmISA::ArmFault | |
| DomainLL enum value | gem5::ArmISA::ArmFault | |
| ec(ThreadContext *tc) const override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| FaultSource enum name | gem5::ArmISA::ArmFault | |
| FaultSourceInvalid enum value | gem5::ArmISA::ArmFault | |
| faultUpdated | gem5::ArmISA::ArmFault | protected |
| fiqDisable(ThreadContext *tc) override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| from64 | gem5::ArmISA::ArmFault | protected |
| fromEL | gem5::ArmISA::ArmFault | protected |
| fromMode | gem5::ArmISA::ArmFault | protected |
| getFaultVAddr(Addr &va) const | gem5::ArmISA::ArmFault | inlinevirtual |
| getFsr(ThreadContext *tc) const | gem5::ArmISA::ArmFault | inlinevirtual |
| getSyndromeReg64() const | gem5::ArmISA::ArmFault | |
| getToMode() const | gem5::ArmISA::ArmFault | inline |
| getVector(ThreadContext *tc) | gem5::ArmISA::ArmFault | protectedvirtual |
| getVector64(ThreadContext *tc) | gem5::ArmISA::ArmFault | protected |
| hypRouted | gem5::ArmISA::ArmFault | protected |
| il(ThreadContext *tc) const override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| instrAnnotate(const StaticInstPtr &inst) | gem5::ArmISA::ArmFault | |
| InstructionCacheMaintenance enum value | gem5::ArmISA::ArmFault | |
| invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override | gem5::ArmISA::ArmSev | virtual |
| invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) | gem5::ArmISA::ArmFault | |
| invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) | gem5::ArmISA::ArmFault | |
| isResetSPSR() | gem5::ArmISA::ArmFault | inline |
| iss() const override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| issRaw | gem5::ArmISA::ArmFault | protected |
| isStage2() const | gem5::ArmISA::ArmFault | inlinevirtual |
| longDescFaultSources | gem5::ArmISA::ArmFault | static |
| LpaeTran enum value | gem5::ArmISA::ArmFault | |
| machInst | gem5::ArmISA::ArmFault | protected |
| name() const override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| nextMode() override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| NODEBUG enum value | gem5::ArmISA::ArmFault | |
| NumFaultSources enum value | gem5::ArmISA::ArmFault | |
| OFA enum value | gem5::ArmISA::ArmFault | |
| offset(ThreadContext *tc) override | gem5::ArmISA::ArmFaultVals< ArmSev > | virtual |
| offset64(ThreadContext *tc) override | gem5::ArmISA::ArmFaultVals< ArmSev > | virtual |
| OVA enum value | gem5::ArmISA::ArmFault | |
| PermissionLL enum value | gem5::ArmISA::ArmFault | |
| PrefetchTLBMiss enum value | gem5::ArmISA::ArmFault | |
| PrefetchUncacheable enum value | gem5::ArmISA::ArmFault | |
| routeToHyp(ThreadContext *tc) const | gem5::ArmISA::ArmFault | inlinevirtual |
| routeToMonitor(ThreadContext *tc) const override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| S1PTW enum value | gem5::ArmISA::ArmFault | |
| SAS enum value | gem5::ArmISA::ArmFault | |
| setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) | gem5::ArmISA::ArmFault | virtual |
| SF enum value | gem5::ArmISA::ArmFault | |
| shortDescFaultSources | gem5::ArmISA::ArmFault | static |
| span | gem5::ArmISA::ArmFault | protected |
| SRT enum value | gem5::ArmISA::ArmFault | |
| SSE enum value | gem5::ArmISA::ArmFault | |
| SynchExtAbtOnTranslTableWalkLL enum value | gem5::ArmISA::ArmFault | |
| SynchPtyErrOnMemoryAccess enum value | gem5::ArmISA::ArmFault | |
| SynchPtyErrOnTranslTableWalkLL enum value | gem5::ArmISA::ArmFault | |
| SynchronousExternalAbort enum value | gem5::ArmISA::ArmFault | |
| thumbPcElrOffset() override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| thumbPcOffset(bool is_hyp) override | gem5::ArmISA::ArmFaultVals< ArmSev > | inlinevirtual |
| TLBConflictAbort enum value | gem5::ArmISA::ArmFault | |
| to64 | gem5::ArmISA::ArmFault | protected |
| toEL | gem5::ArmISA::ArmFault | protected |
| toMode | gem5::ArmISA::ArmFault | protected |
| TranMethod enum name | gem5::ArmISA::ArmFault | |
| TranslationLL enum value | gem5::ArmISA::ArmFault | |
| UnknownTran enum value | gem5::ArmISA::ArmFault | |
| update(ThreadContext *tc) | gem5::ArmISA::ArmFault | |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protectedstatic |
| vals("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, ExceptionClass::SVC_TO_HYP) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, ExceptionClass::SMC_TO_HYP) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, ExceptionClass::HVC) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, ExceptionClass::PREFETCH_ABORT_TO_HYP) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, ExceptionClass::DATA_ABORT_TO_HYP) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, ExceptionClass::INVALID) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, ExceptionClass::INVALID) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, ExceptionClass::INVALID) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, ExceptionClass::ILLEGAL_INST) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::PC_ALIGNMENT) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::STACK_PTR_ALIGNMENT) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::SERROR) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_BREAKPOINT) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::HW_BREAKPOINT) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::WATCHPOINT) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_STEP) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN) | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| vals | gem5::ArmISA::ArmFaultVals< ArmSev > | protected |
| VECTORCATCH enum value | gem5::ArmISA::ArmFault | |
| vectorCatch(ThreadContext *tc, const StaticInstPtr &inst) | gem5::ArmISA::ArmFault | |
| vectorCatchFlag() const | gem5::ArmISA::ArmFault | inlinevirtual |
| VmsaTran enum value | gem5::ArmISA::ArmFault | |
| WPOINT_CM enum value | gem5::ArmISA::ArmFault | |
| WPOINT_NOCM enum value | gem5::ArmISA::ArmFault | |
| ~FaultBase() | gem5::FaultBase | inlinevirtual |