gem5  v21.2.0.0
gem5::ArmISA::VirtualFastInterrupt Member List

This is the complete list of members for gem5::ArmISA::VirtualFastInterrupt, including all inherited members.

aarch64FaultSourcesgem5::ArmISA::ArmFaultstatic
abortDisable(ThreadContext *tc) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
AccessFlagLL enum valuegem5::ArmISA::ArmFault
AddressSizeLL enum valuegem5::ArmISA::ArmFault
AlignmentFault enum valuegem5::ArmISA::ArmFault
annotate(AnnotationIDs id, uint64_t val)gem5::ArmISA::ArmFaultinlinevirtual
AnnotationIDs enum namegem5::ArmISA::ArmFault
AR enum valuegem5::ArmISA::ArmFault
ArmFault(ExtMachInst _machInst=0, uint32_t _iss=0)gem5::ArmISA::ArmFaultinline
ArmFaultVals(ExtMachInst _machInst=0, uint32_t _iss=0)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inline
armPcElrOffset() overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
armPcOffset(bool isHyp) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
AsynchPtyErrOnMemoryAccess enum valuegem5::ArmISA::ArmFault
AsynchronousExternalAbort enum valuegem5::ArmISA::ArmFault
BRKPOINT enum valuegem5::ArmISA::ArmFault
bStepgem5::ArmISA::ArmFaultprotected
CM enum valuegem5::ArmISA::ArmFault
DebugEvent enum valuegem5::ArmISA::ArmFault
DebugType enum namegem5::ArmISA::ArmFault
DomainLL enum valuegem5::ArmISA::ArmFault
ec(ThreadContext *tc) const overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
FaultSource enum namegem5::ArmISA::ArmFault
FaultSourceInvalid enum valuegem5::ArmISA::ArmFault
faultUpdatedgem5::ArmISA::ArmFaultprotected
fiqDisable(ThreadContext *tc) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
from64gem5::ArmISA::ArmFaultprotected
fromELgem5::ArmISA::ArmFaultprotected
fromModegem5::ArmISA::ArmFaultprotected
getFaultAddrReg64() constgem5::ArmISA::ArmFault
getFaultVAddr(Addr &va) constgem5::ArmISA::ArmFaultinlinevirtual
getFsr(ThreadContext *tc) constgem5::ArmISA::ArmFaultinlinevirtual
getSyndromeReg64() constgem5::ArmISA::ArmFault
getToMode() constgem5::ArmISA::ArmFaultinline
getVector(ThreadContext *tc)gem5::ArmISA::ArmFaultprotectedvirtual
getVector64(ThreadContext *tc)gem5::ArmISA::ArmFaultprotected
hypRoutedgem5::ArmISA::ArmFaultprotected
instrAnnotate(const StaticInstPtr &inst)gem5::ArmISA::ArmFault
InstructionCacheMaintenance enum valuegem5::ArmISA::ArmFault
invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) overridegem5::ArmISA::ArmFaultvirtual
invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)gem5::ArmISA::ArmFault
invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)gem5::ArmISA::ArmFault
isResetSPSR()gem5::ArmISA::ArmFaultinline
iss() const overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inline
gem5::ArmISA::ArmFault::iss() const =0gem5::ArmISA::ArmFaultpure virtual
issRawgem5::ArmISA::ArmFaultprotected
isStage2() constgem5::ArmISA::ArmFaultinlinevirtual
longDescFaultSourcesgem5::ArmISA::ArmFaultstatic
LpaeTran enum valuegem5::ArmISA::ArmFault
machInstgem5::ArmISA::ArmFaultprotected
name() const overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inline
gem5::ArmISA::ArmFault::name() const =0gem5::FaultBasepure virtual
nextMode() overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
NODEBUG enum valuegem5::ArmISA::ArmFault
NumFaultSources enum valuegem5::ArmISA::ArmFault
OFA enum valuegem5::ArmISA::ArmFault
offset(ThreadContext *tc) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >virtual
offset64(ThreadContext *tc) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >virtual
OVA enum valuegem5::ArmISA::ArmFault
PermissionLL enum valuegem5::ArmISA::ArmFault
PrefetchTLBMiss enum valuegem5::ArmISA::ArmFault
PrefetchUncacheable enum valuegem5::ArmISA::ArmFault
routeToHyp(ThreadContext *tc) constgem5::ArmISA::ArmFaultinlinevirtual
routeToMonitor(ThreadContext *tc) const overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
S1PTW enum valuegem5::ArmISA::ArmFault
SAS enum valuegem5::ArmISA::ArmFault
setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)gem5::ArmISA::ArmFaultvirtual
SF enum valuegem5::ArmISA::ArmFault
shortDescFaultSourcesgem5::ArmISA::ArmFaultstatic
spangem5::ArmISA::ArmFaultprotected
SRT enum valuegem5::ArmISA::ArmFault
SSE enum valuegem5::ArmISA::ArmFault
SynchExtAbtOnTranslTableWalkLL enum valuegem5::ArmISA::ArmFault
SynchPtyErrOnMemoryAccess enum valuegem5::ArmISA::ArmFault
SynchPtyErrOnTranslTableWalkLL enum valuegem5::ArmISA::ArmFault
SynchronousExternalAbort enum valuegem5::ArmISA::ArmFault
thumbPcElrOffset() overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
thumbPcOffset(bool isHyp) overridegem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >inlinevirtual
TLBConflictAbort enum valuegem5::ArmISA::ArmFault
to64gem5::ArmISA::ArmFaultprotected
toELgem5::ArmISA::ArmFaultprotected
toModegem5::ArmISA::ArmFaultprotected
TranMethod enum namegem5::ArmISA::ArmFault
TranslationLL enum valuegem5::ArmISA::ArmFault
UnknownTran enum valuegem5::ArmISA::ArmFault
update(ThreadContext *tc)gem5::ArmISA::ArmFault
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protectedstatic
vals("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, EC_HVC)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_INVALID)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_INVALID)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_INVALID)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_WATCHPOINT)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vals("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
valsgem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >protected
vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)gem5::ArmISA::ArmFault
VECTORCATCH enum valuegem5::ArmISA::ArmFault
vectorCatchFlag() constgem5::ArmISA::ArmFaultinlinevirtual
VirtualFastInterrupt()gem5::ArmISA::VirtualFastInterrupt
VmsaTran enum valuegem5::ArmISA::ArmFault
WPOINT_CM enum valuegem5::ArmISA::ArmFault
WPOINT_NOCM enum valuegem5::ArmISA::ArmFault
~FaultBase()gem5::FaultBaseinlinevirtual

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