_drainManager | gem5::Drainable | private |
_drainState | gem5::Drainable | mutableprivate |
_name | gem5::Named | private |
_objNameResolver | gem5::SimObject | privatestatic |
_params | gem5::SimObject | protected |
_regClasses | gem5::BaseISA | protected |
addStat(statistics::Info *info) | gem5::statistics::Group | |
addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
BaseISA(const SimObjectParams &p, const std::string &name) | gem5::BaseISA | inlineprotected |
clear() | gem5::BaseISA | inlinevirtual |
copyRegsFrom(ThreadContext *src) override | gem5::Iris::ISA | |
gem5::BaseISA::copyRegsFrom(ThreadContext *src)=0 | gem5::BaseISA | pure virtual |
currentSection() | gem5::Serializable | static |
deschedule(Event &event) | gem5::EventManager | inline |
deschedule(Event *event) | gem5::EventManager | inline |
dmDrain() | gem5::Drainable | private |
dmDrainResume() | gem5::Drainable | private |
drain() override | gem5::SimObject | inlinevirtual |
Drainable() | gem5::Drainable | protected |
drainResume() | gem5::Drainable | inlineprotectedvirtual |
drainState() const | gem5::Drainable | inline |
EventManager(EventManager &em) | gem5::EventManager | inline |
EventManager(EventManager *em) | gem5::EventManager | inline |
EventManager(EventQueue *eq) | gem5::EventManager | inline |
eventq | gem5::EventManager | protected |
eventQueue() const | gem5::EventManager | inline |
find(const char *name) | gem5::SimObject | static |
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
getExecutingAsid() const | gem5::BaseISA | inlinevirtual |
getIsaName() const | gem5::BaseISA | inline |
getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
getProbeManager() | gem5::SimObject | |
getSimObjectResolver() | gem5::SimObject | static |
getStatGroups() const | gem5::statistics::Group | |
getStats() const | gem5::statistics::Group | |
getVectorLengthInBytes() const | gem5::BaseISA | inlinevirtual |
globalClearExclusive() | gem5::BaseISA | inlinevirtual |
globalClearExclusive(ExecContext *xc) | gem5::BaseISA | inlinevirtual |
Group()=delete | gem5::statistics::Group | |
Group(const Group &)=delete | gem5::statistics::Group | |
Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
handleLockedRead(const RequestPtr &req) | gem5::BaseISA | inlinevirtual |
handleLockedRead(ExecContext *xc, const RequestPtr &req) | gem5::BaseISA | inlinevirtual |
handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) | gem5::BaseISA | inlinevirtual |
handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) | gem5::BaseISA | inlinevirtual |
handleLockedSnoopHit() | gem5::BaseISA | inlinevirtual |
handleLockedSnoopHit(ExecContext *xc) | gem5::BaseISA | inlinevirtual |
handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) | gem5::BaseISA | inlinevirtual |
handleLockedWrite(ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) | gem5::BaseISA | inlinevirtual |
init() | gem5::SimObject | virtual |
initState() | gem5::SimObject | virtual |
inUserMode() const override | gem5::Iris::ISA | inlinevirtual |
ISA(const Params &p) | gem5::Iris::ISA | inline |
isaName | gem5::BaseISA | protected |
loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
memInvalidate() | gem5::SimObject | inlinevirtual |
memWriteback() | gem5::SimObject | inlinevirtual |
mergedParent | gem5::statistics::Group | private |
mergedStatGroups | gem5::statistics::Group | private |
mergeStatGroup(Group *block) | gem5::statistics::Group | |
name() const | gem5::Named | inlinevirtual |
Named(const std::string &name_) | gem5::Named | inline |
newPCState(Addr new_inst_addr=0) const override | gem5::Iris::ISA | inlinevirtual |
notifyFork() | gem5::Drainable | inlinevirtual |
operator=(const Group &)=delete | gem5::statistics::Group | |
Params typedef | gem5::SimObject | |
params() const | gem5::SimObject | inline |
path | gem5::Serializable | privatestatic |
preDumpStats() | gem5::statistics::Group | virtual |
probeManager | gem5::SimObject | private |
readMiscReg(RegIndex idx) override | gem5::Iris::ISA | inlinevirtual |
readMiscRegNoEffect(RegIndex idx) const override | gem5::Iris::ISA | inlinevirtual |
RegClasses typedef | gem5::BaseISA | |
regClasses() const | gem5::BaseISA | inline |
regProbeListeners() | gem5::SimObject | virtual |
regProbePoints() | gem5::SimObject | virtual |
regStats() | gem5::statistics::Group | virtual |
reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
resetStats() | gem5::statistics::Group | virtual |
resetThread() | gem5::BaseISA | inlinevirtual |
resolveStat(std::string name) const | gem5::statistics::Group | |
schedule(Event &event, Tick when) | gem5::EventManager | inline |
schedule(Event *event, Tick when) | gem5::EventManager | inline |
Serializable() | gem5::Serializable | |
serialize(CheckpointOut &cp) const override | gem5::Iris::ISA | virtual |
serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
setCurTick(Tick newVal) | gem5::EventManager | inline |
setMiscReg(RegIndex idx, RegVal val) override | gem5::Iris::ISA | inlinevirtual |
setMiscRegNoEffect(RegIndex idx, RegVal val) override | gem5::Iris::ISA | inlinevirtual |
setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
setThreadContext(ThreadContext *_tc) | gem5::BaseISA | inlinevirtual |
signalDrainDone() const | gem5::Drainable | inlineprotected |
SimObject(const Params &p) | gem5::SimObject | |
SimObjectList typedef | gem5::SimObject | private |
simObjectList | gem5::SimObject | privatestatic |
startup() | gem5::SimObject | virtual |
statGroups | gem5::statistics::Group | private |
stats | gem5::statistics::Group | private |
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) | gem5::BaseISA | inlinevirtual |
tc | gem5::BaseISA | protected |
unserialize(CheckpointIn &cp) override | gem5::SimObject | inlinevirtual |
unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
~Drainable() | gem5::Drainable | protectedvirtual |
~Group() | gem5::statistics::Group | virtual |
~Named()=default | gem5::Named | virtual |
~Serializable() | gem5::Serializable | virtual |
~SimObject() | gem5::SimObject | virtual |