gem5  v21.1.0.2
Functions | Variables
The SimObject API.

These methods relate to the SimObject interface. More...

Functions

const Paramsgem5::SimObject::params () const
 
 gem5::SimObject::SimObject (const Params &p)
 
virtual void gem5::SimObject::init ()
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
virtual void gem5::SimObject::regProbePoints ()
 Register probe points for this object. More...
 
virtual void gem5::SimObject::regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergem5::SimObject::getProbeManager ()
 Get the probe manager for this object. More...
 
virtual Portgem5::SimObject::getPort (const std::string &if_name, PortID idx=InvalidPortID)
 Get a port with a given name and index. More...
 
virtual void gem5::SimObject::startup ()
 startup() is the final initialization call before simulation. More...
 
virtual void gem5::SimObject::memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void gem5::SimObject::memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
static SimObjectgem5::SimObject::find (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 

Variables

const SimObjectParams & gem5::SimObject::_params
 Cached copy of the object parameters. More...
 

Detailed Description

These methods relate to the SimObject interface.

Function Documentation

◆ find()

SimObject * gem5::SimObject::find ( const char *  name)
static

Find the SimObject with the given name and return a pointer to it.

Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.

Definition at line 176 of file sim_object.cc.

References gem5::ArmISA::i, gem5::Named::name(), and gem5::SimObject::simObjectList.

Referenced by gem5::LdsState::getLdsChunk(), gem5::X86KvmCPU::getMsrIntersection(), gem5::LdsState::releaseSpace(), and gem5::LdsState::reserveSpace().

◆ getPort()

Port & gem5::SimObject::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
virtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented in gem5::SMMUv3, gem5::SMMUv3DeviceInterface, gem5::memory::qos::MemSinkCtrl, gem5::BaseCache, gem5::ArmISA::TableWalker, gem5::memory::MemCtrl, gem5::IGbE, gem5::BaseXBar, gem5::memory::CfiMemory, gem5::NSGigE, gem5::SimpleCache, gem5::Bridge, gem5::X86ISA::GpuTLB, gem5::System, gem5::BaseTrafficGen, gem5::SimpleMemobj, gem5::DmaDevice, gem5::ruby::GPUCoalescer, gem5::sinic::Device, gem5::X86ISA::Interrupts, gem5::DistEtherLink, gem5::BaseCPU, gem5::memory::DRAMsim3, gem5::memory::DRAMSim2, gem5::ArmSigInterruptPinGen, gem5::memory::SimpleMemory, gem5::TLBCoalescer, gem5::CopyEngine, gem5::RiscvISA::Walker, gem5::X86ISA::Walker, gem5::ruby::RubyPort, gem5::EtherLink, gem5::Clint, gem5::PioDevice, gem5::ExternalSlave, gem5::X86ISA::I8042, gem5::fastmodel::GIC, gem5::ProtocolTester, gem5::ExternalMaster, gem5::X86ISA::I82094AA, gem5::fastmodel::CortexA76Cluster, gem5::RubyTester, gem5::fastmodel::CortexR52Cluster, gem5::EtherTapBase, gem5::X86ISA::I8259, gem5::X86ISA::Cmos, gem5::CommMonitor, gem5::MemTest, gem5::fastmodel::CortexA76, gem5::RiscvRTC, gem5::fastmodel::CortexR52, gem5::X86ISA::I8254, gem5::RubyDirectedTester, gem5::MemDelay, gem5::MemCheckerMonitor, gem5::EtherBus, gem5::GarnetSyntheticTraffic, gem5::AddrMapper, gem5::EtherSwitch, gem5::SerialLink, gem5::ruby::AbstractController, gem5::ComputeUnit, gem5::scmi::Platform, gem5::Gicv3Its, gem5::LdsState, gem5::ruby::MessageBuffer, and gem5::ruby::Network.

Definition at line 126 of file sim_object.cc.

References fatal, and gem5::Named::name().

Referenced by gem5::CxxConfigManager::bindPort(), gem5::EtherSwitch::getPort(), gem5::AddrMapper::getPort(), gem5::GarnetSyntheticTraffic::getPort(), gem5::MemCheckerMonitor::getPort(), gem5::MemDelay::getPort(), gem5::RubyDirectedTester::getPort(), gem5::fastmodel::CortexR52::getPort(), gem5::MemTest::getPort(), gem5::CommMonitor::getPort(), gem5::EtherTapBase::getPort(), gem5::fastmodel::CortexR52Cluster::getPort(), gem5::fastmodel::CortexA76Cluster::getPort(), gem5::RubyTester::getPort(), gem5::SMMUv3DeviceInterface::getPort(), gem5::ExternalMaster::getPort(), gem5::ProtocolTester::getPort(), gem5::ExternalSlave::getPort(), gem5::PioDevice::getPort(), gem5::EtherLink::getPort(), gem5::memory::qos::MemSinkCtrl::getPort(), gem5::ruby::RubyPort::getPort(), gem5::RiscvISA::Walker::getPort(), gem5::X86ISA::Walker::getPort(), gem5::memory::SimpleMemory::getPort(), gem5::ArmSigInterruptPinGen::getPort(), gem5::SMMUv3::getPort(), gem5::memory::DRAMSim2::getPort(), gem5::memory::DRAMsim3::getPort(), gem5::BaseCPU::getPort(), gem5::X86ISA::Interrupts::getPort(), gem5::DistEtherLink::getPort(), gem5::BaseTrafficGen::getPort(), gem5::SimpleMemobj::getPort(), gem5::scmi::Platform::getPort(), gem5::SerialLink::getPort(), gem5::Bridge::getPort(), gem5::SimpleCache::getPort(), gem5::memory::CfiMemory::getPort(), gem5::BaseXBar::getPort(), gem5::memory::MemCtrl::getPort(), gem5::ComputeUnit::getPort(), gem5::ArmISA::TableWalker::getPort(), and gem5::BaseCache::getPort().

◆ getProbeManager()

ProbeManager * gem5::SimObject::getProbeManager ( )

◆ init()

void gem5::SimObject::init ( )
virtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented in gem5::memory::NVMInterface, gem5::BaseCache, gem5::branch_prediction::MultiperspectivePerceptron, gem5::memory::DRAMInterface, gem5::memory::MemCtrl, gem5::IGbE, gem5::ComputeUnit, gem5::memory::CfiMemory, gem5::Bridge, gem5::BaseCPU, gem5::branch_prediction::StatisticalCorrector, gem5::branch_prediction::LoopPredictor, gem5::BaseTrafficGen, gem5::RangeAddrMapper, gem5::DmaDevice, gem5::branch_prediction::MultiperspectivePerceptronTAGE, gem5::DistEtherLink, gem5::memory::DRAMsim3, gem5::X86ISA::Interrupts, gem5::memory::DRAMSim2, gem5::o3::CPU, gem5::memory::SimpleMemory, gem5::SMMUv3, gem5::CpuLocalTimer, gem5::memory::qos::MemSinkCtrl, gem5::ruby::RubyPort, gem5::Clint, gem5::ExternalSlave, gem5::EnergyCtrl, gem5::PioDevice, gem5::MinorCPU, gem5::Plic, gem5::ExternalMaster, gem5::TrafficGen, gem5::ProtocolTester, gem5::Gicv3, gem5::RubyTester, gem5::Iris::BaseCPU, gem5::ruby::RubySystem, gem5::BaseSimpleCPU, gem5::X86ISA::I82094AA, gem5::CheckerCPU, gem5::BaseKvmCPU, gem5::ArmISA::MMU, gem5::memory::qos::Policy, gem5::BaseGic, gem5::RubyDirectedTester, gem5::CommMonitor, gem5::branch_prediction::LTAGE, gem5::Process, gem5::MemCheckerMonitor, gem5::memory::qos::FixedPriorityPolicy, gem5::MemDelay, gem5::branch_prediction::TAGEBase, gem5::AddrMapper, gem5::ruby::DMASequencer, gem5::GarnetSyntheticTraffic, gem5::AtomicSimpleCPU, gem5::TimingSimpleCPU, gem5::NoMaliGpu, gem5::Pc, sc_gem5::Kernel, gem5::X86ISA::I8259, gem5::CoherentXBar, gem5::SerialLink, gem5::Wavefront, gem5::Shader, gem5::TraceCPU, gem5::ruby::garnet::GarnetExtLink, gem5::SimPoint, gem5::ruby::AbstractController, gem5::ruby::Switch, gem5::ruby::RubyPortProxy, gem5::ruby::garnet::Router, gem5::ruby::CacheMemory, gem5::ruby::SimpleNetwork, gem5::ruby::garnet::GarnetNetwork, gem5::ruby::DirectoryMemory, gem5::ruby::WireBuffer, gem5::ruby::garnet::GarnetIntLink, gem5::ruby::BasicLink, gem5::EtherDump, and gem5::ruby::BasicRouter.

Definition at line 76 of file sim_object.cc.

Referenced by gem5::ruby::garnet::GarnetNetwork::init(), gem5::ruby::SimpleNetwork::init(), gem5::branch_prediction::LTAGE::init(), gem5::memory::qos::MemSinkCtrl::init(), gem5::memory::SimpleMemory::init(), gem5::memory::DRAMSim2::init(), gem5::memory::DRAMsim3::init(), gem5::BaseTrafficGen::init(), gem5::memory::CfiMemory::init(), gem5::CoherentXBar::init(), gem5::memory::DRAMInterface::init(), gem5::memory::NVMInterface::init(), gem5::CxxConfigManager::instantiate(), and gem5::BaseTags::BaseTagStats::regStats().

◆ memInvalidate()

virtual void gem5::SimObject::memInvalidate ( )
inlinevirtual

Invalidate the contents of memory buffers.

When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.

@warn This does not cause any dirty state to be written back to memory.

Reimplemented in gem5::BaseCache, and gem5::BaseTLB.

Definition at line 313 of file sim_object.hh.

◆ memWriteback()

virtual void gem5::SimObject::memWriteback ( )
inlinevirtual

Write back dirty buffers to memory using functional writes.

After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.

Reimplemented in gem5::BaseCache, gem5::MinorCPU, and gem5::ruby::RubySystem.

Definition at line 298 of file sim_object.hh.

◆ params()

const Params& gem5::SimObject::params ( ) const
inline
Returns
This function returns the cached copy of the object parameters.

Definition at line 176 of file sim_object.hh.

References gem5::SimObject::_params.

Referenced by gem5::ruby::Switch::addOutPort(), gem5::ArmProcess::ArmProcess(), gem5::branch_prediction::BPredUnit::BPredUnit(), gem5::ArmISA::ISA::clear(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::VirtIO9PSocket::connectSocket(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::Iris::CPU< CortexA76TC >::CPU(), gem5::GenericTimer::createTimers(), gem5::SMMUv3DeviceInterface::drain(), gem5::ArmISA::TableWalker::drainResume(), gem5::pseudo_inst::dumpresetstats(), gem5::pseudo_inst::dumpstats(), gem5::MaltaIO::frequency(), gem5::ArmPPIGen::get(), gem5::System::getGuestByteOrder(), gem5::replacement_policy::Dueling::getVictim(), gem5::IdeController::IdeController(), gem5::ruby::AbstractController::init(), gem5::MinorCPU::init(), gem5::CpuLocalTimer::init(), gem5::BaseCPU::init(), gem5::branch_prediction::MultiperspectivePerceptron::init(), gem5::RiscvISA::FsLinux::initState(), gem5::fastmodel::CortexA76::initState(), gem5::ArmISA::FsFreebsd::initState(), gem5::KernelWorkload::initState(), gem5::ArmISA::FsLinux::initState(), gem5::ArmISA::FsWorkload::initState(), gem5::memory::AbstractMemory::initState(), gem5::Iob::Iob(), gem5::memory::AbstractMemory::isNull(), gem5::KernelWorkload::KernelWorkload(), gem5::KvmVM::KvmVM(), gem5::LdsState::LdsState(), gem5::pseudo_inst::loadsymbol(), gem5::pseudo_inst::m5checkpoint(), gem5::MinorCPU::MinorCPU(), gem5::MipsProcess::MipsProcess(), gem5::CommMonitor::MonitorStats::MonitorStats(), gem5::ruby::Network::Network(), gem5::RawDiskImage::notifyFork(), gem5::CowDiskImage::notifyFork(), gem5::PowerProcess::PowerProcess(), gem5::Process::Process(), gem5::AmbaFake::read(), gem5::IsaFake::read(), gem5::RealViewCtrl::read(), gem5::NSGigE::read(), gem5::pseudo_inst::readfile(), gem5::ruby::RubySystem::registerRequestorIDs(), gem5::BaseMemProbe::regProbeListeners(), gem5::sinic::Device::reset(), gem5::pseudo_inst::resetstats(), gem5::RiscvProcess::RiscvProcess(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexR52::setCluster(), gem5::fastmodel::CortexA76::setCluster(), gem5::CheckerCPU::setSystem(), gem5::ArmISA::PMU::setThreadContext(), gem5::SimpleCache::SimpleCache(), gem5::branch_prediction::SimpleIndirectPredictor::SimpleIndirectPredictor(), gem5::SMMUv3::SMMUv3(), gem5::SparcProcess::SparcProcess(), gem5::StackDistProbe::StackDistProbeStats::StackDistProbeStats(), gem5::VirtIO9PDiod::startDiod(), gem5::BaseArmKvmCPU::startup(), gem5::BaseKvmCPU::startup(), gem5::ArmISA::FsLinux::startup(), gem5::Root::startup(), gem5::BaseCPU::startup(), gem5::BaseKvmCPU::startupThread(), gem5::System::System(), gem5::ruby::Topology::Topology(), gem5::Process::tryLoaders(), gem5::VirtIO9PBase::VirtIO9PBase(), gem5::pseudo_inst::workbegin(), gem5::pseudo_inst::workend(), gem5::AmbaFake::write(), gem5::IsaFake::write(), gem5::X86ISA::ACPI::RSDP::write(), gem5::IGbE::write(), and gem5::X86ISA::ACPI::SysDescTable::writeBuf().

◆ regProbeListeners()

void gem5::SimObject::regProbeListeners ( )
virtual

Register probe listeners for this object.

No probe listeners by default, so do nothing in base.

Reimplemented in gem5::prefetch::Base, gem5::compression::FrequentValues, gem5::ArmISA::PMU, gem5::BaseMemProbe, gem5::o3::SimpleTrace, gem5::o3::ElasticTrace, and gem5::SimPoint.

Definition at line 115 of file sim_object.cc.

Referenced by gem5::CxxConfigManager::instantiate().

◆ regProbePoints()

void gem5::SimObject::regProbePoints ( )
virtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented in gem5::BaseCache, gem5::ArmISA::TLB, gem5::BaseCPU, gem5::AtomicSimpleCPU, gem5::o3::CPU, gem5::CommMonitor, gem5::branch_prediction::BPredUnit, and gem5::PowerModel.

Definition at line 107 of file sim_object.cc.

Referenced by gem5::CxxConfigManager::instantiate().

◆ SimObject()

gem5::SimObject::SimObject ( const Params p)

Definition at line 58 of file sim_object.cc.

References gem5::SimObject::probeManager, and gem5::SimObject::simObjectList.

◆ startup()

void gem5::SimObject::startup ( )
virtual

Variable Documentation

◆ _params

const SimObjectParams& gem5::SimObject::_params
protected

Cached copy of the object parameters.

Definition at line 167 of file sim_object.hh.

Referenced by gem5::PMAChecker::params(), gem5::BaseGic::params(), and gem5::SimObject::params().


Generated on Tue Sep 21 2021 12:27:00 for gem5 by doxygen 1.8.17