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gem5
v22.1.0.0
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These methods relate to the SimObject interface. More...
Functions | |
| const Params & | gem5::SimObject::params () const |
| gem5::SimObject::SimObject (const Params &p) | |
| virtual void | gem5::SimObject::init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
| virtual void | gem5::SimObject::regProbePoints () |
| Register probe points for this object. More... | |
| virtual void | gem5::SimObject::regProbeListeners () |
| Register probe listeners for this object. More... | |
| ProbeManager * | gem5::SimObject::getProbeManager () |
| Get the probe manager for this object. More... | |
| virtual Port & | gem5::SimObject::getPort (const std::string &if_name, PortID idx=InvalidPortID) |
| Get a port with a given name and index. More... | |
| virtual void | gem5::SimObject::startup () |
| startup() is the final initialization call before simulation. More... | |
| virtual void | gem5::SimObject::memWriteback () |
| Write back dirty buffers to memory using functional writes. More... | |
| virtual void | gem5::SimObject::memInvalidate () |
| Invalidate the contents of memory buffers. More... | |
| static SimObject * | gem5::SimObject::find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. More... | |
Variables | |
| const SimObjectParams & | gem5::SimObject::_params |
| Cached copy of the object parameters. More... | |
These methods relate to the SimObject interface.
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static |
Find the SimObject with the given name and return a pointer to it.
Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.
Definition at line 176 of file sim_object.cc.
References gem5::ArmISA::i, and gem5::SimObject::simObjectList.
Referenced by gem5::LdsState::getLdsChunk(), gem5::X86KvmCPU::getMsrIntersection(), gem5::LdsState::releaseSpace(), and gem5::LdsState::reserveSpace().
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Get a port with a given name and index.
This is used at binding time and returns a reference to a protocol-agnostic port.
gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.
| if_name | Port name |
| idx | Index in the case of a VectorPort |
Reimplemented in gem5::SMMUv3, gem5::SMMUv3DeviceInterface, gem5::memory::qos::MemSinkCtrl, gem5::System, gem5::BaseXBar, gem5::ThreadBridge, gem5::SysBridge, gem5::memory::SimpleMemory, gem5::ruby::RubyPort, gem5::ruby::GPUCoalescer, gem5::PortTerminator, gem5::MemDelay, gem5::memory::MemCtrl, gem5::MemCheckerMonitor, gem5::ExternalSlave, gem5::ExternalMaster, gem5::memory::DRAMsim3, gem5::memory::DRAMSim2, gem5::CommMonitor, gem5::memory::CfiMemory, gem5::BaseCache, gem5::Bridge, gem5::AddrMapper, gem5::SimpleMemobj, gem5::SimpleCache, gem5::X86IdeController, gem5::X86ISA::I8259, gem5::X86ISA::I8254, gem5::X86ISA::I82094AA, gem5::X86ISA::I8042, gem5::X86ISA::Cmos, gem5::RiscvRTC, gem5::Clint, gem5::CopyEngine, gem5::sinic::Device, gem5::NSGigE, gem5::IGbE, gem5::EtherTapBase, gem5::EtherSwitch, gem5::EtherLink, gem5::EtherBus, gem5::DistEtherLink, gem5::PioDevice, gem5::DmaDevice, gem5::ArmSigInterruptPinGen, gem5::GUPSGen, gem5::BaseTrafficGen, gem5::RubyTester, gem5::MemTest, gem5::ProtocolTester, gem5::GarnetSyntheticTraffic, gem5::RubyDirectedTester, gem5::BaseCPU, gem5::X86ISA::Walker, gem5::X86ISA::Interrupts, gem5::RiscvISA::Walker, gem5::ArmISA::TableWalker, gem5::fastmodel::GIC, gem5::fastmodel::CortexR52Cluster, gem5::fastmodel::CortexR52, gem5::fastmodel::CortexA76Cluster, gem5::fastmodel::CortexA76, gem5::VegaTLBCoalescer, gem5::VegaISA::GpuTLB, gem5::VegaISA::Walker, gem5::TLBCoalescer, gem5::X86ISA::GpuTLB, gem5::SerialLink, gem5::ruby::AbstractController, gem5::ComputeUnit, gem5::Gicv3Its, gem5::scmi::Platform, gem5::AMDGPUMemoryManager, gem5::OutgoingRequestBridge, gem5::LdsState, gem5::fastmodel::ResetControllerExample, gem5::ruby::Network, and gem5::ruby::MessageBuffer.
Definition at line 126 of file sim_object.cc.
References fatal, and gem5::Named::name().
Referenced by gem5::CxxConfigManager::bindPort(), gem5::AMDGPUMemoryManager::getPort(), gem5::scmi::Platform::getPort(), gem5::ComputeUnit::getPort(), gem5::SerialLink::getPort(), gem5::VegaISA::Walker::getPort(), gem5::fastmodel::CortexA76Cluster::getPort(), gem5::fastmodel::CortexR52::getPort(), gem5::fastmodel::CortexR52Cluster::getPort(), gem5::ArmISA::TableWalker::getPort(), gem5::RiscvISA::Walker::getPort(), gem5::X86ISA::Interrupts::getPort(), gem5::X86ISA::Walker::getPort(), gem5::BaseCPU::getPort(), gem5::RubyDirectedTester::getPort(), gem5::GarnetSyntheticTraffic::getPort(), gem5::ProtocolTester::getPort(), gem5::MemTest::getPort(), gem5::RubyTester::getPort(), gem5::BaseTrafficGen::getPort(), gem5::GUPSGen::getPort(), gem5::ArmSigInterruptPinGen::getPort(), gem5::PioDevice::getPort(), gem5::DistEtherLink::getPort(), gem5::EtherLink::getPort(), gem5::EtherSwitch::getPort(), gem5::EtherTapBase::getPort(), gem5::SimpleCache::getPort(), gem5::SimpleMemobj::getPort(), gem5::AddrMapper::getPort(), gem5::Bridge::getPort(), gem5::BaseCache::getPort(), gem5::memory::CfiMemory::getPort(), gem5::CommMonitor::getPort(), gem5::memory::DRAMSim2::getPort(), gem5::memory::DRAMsim3::getPort(), gem5::ExternalMaster::getPort(), gem5::ExternalSlave::getPort(), gem5::MemCheckerMonitor::getPort(), gem5::memory::MemCtrl::getPort(), gem5::MemDelay::getPort(), gem5::PortTerminator::getPort(), gem5::ruby::RubyPort::getPort(), gem5::memory::SimpleMemory::getPort(), gem5::SysBridge::getPort(), gem5::ThreadBridge::getPort(), gem5::BaseXBar::getPort(), gem5::memory::qos::MemSinkCtrl::getPort(), gem5::SMMUv3DeviceInterface::getPort(), and gem5::SMMUv3::getPort().
| ProbeManager * gem5::SimObject::getProbeManager | ( | ) |
Get the probe manager for this object.
Probes generate traces. A trace is a file that keeps a log of events. For example, we can have a probe listener for an address and the trace will be a file that has time stamps for all the reads and writes to that address.
Definition at line 120 of file sim_object.cc.
References gem5::SimObject::probeManager.
Referenced by gem5::prefetch::Base::addEventProbe(), gem5::prefetch::PIF::addEventProbeRetiredInsts(), gem5::BaseCPU::pmuProbePoint(), gem5::branch_prediction::BPredUnit::pmuProbePoint(), gem5::compression::FrequentValues::regProbeListeners(), gem5::prefetch::Base::regProbeListeners(), gem5::o3::Commit::regProbePoints(), gem5::o3::Fetch::regProbePoints(), gem5::o3::IEW::regProbePoints(), gem5::o3::Rename::regProbePoints(), gem5::PowerModel::regProbePoints(), gem5::ArmISA::TLB::regProbePoints(), gem5::BaseCPU::regProbePoints(), gem5::o3::CPU::regProbePoints(), gem5::AtomicSimpleCPU::regProbePoints(), gem5::BaseCache::regProbePoints(), gem5::CommMonitor::regProbePoints(), and gem5::ThermalDomain::setSubSystem().
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init() is called after all C++ SimObjects have been created and all ports are connected.
Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.
Reimplemented in sc_gem5::Kernel, gem5::Process, gem5::memory::SimpleMemory, gem5::ruby::RubySystem, gem5::ruby::RubyPort, gem5::ruby::DMASequencer, gem5::memory::qos::FixedPriorityPolicy, gem5::memory::qos::Policy, gem5::memory::qos::MemSinkCtrl, gem5::memory::NVMInterface, gem5::MemDelay, gem5::memory::MemCtrl, gem5::MemCheckerMonitor, gem5::memory::HBMCtrl, gem5::ExternalSlave, gem5::ExternalMaster, gem5::memory::DRAMsim3, gem5::memory::DRAMSim2, gem5::memory::DRAMInterface, gem5::CommMonitor, gem5::memory::CfiMemory, gem5::BaseCache, gem5::Bridge, gem5::RangeAddrMapper, gem5::AddrMapper, gem5::ComputeUnit, gem5::Pc, gem5::X86ISA::I8259, gem5::X86ISA::I82094AA, gem5::Plic, gem5::Clint, gem5::IGbE, gem5::DistEtherLink, gem5::PioDevice, gem5::DmaDevice, gem5::CpuLocalTimer, gem5::SMMUv3, gem5::NoMaliGpu, gem5::Gicv3, gem5::EnergyCtrl, gem5::BaseGic, gem5::TrafficGen, gem5::GUPSGen, gem5::BaseTrafficGen, gem5::RubyTester, gem5::ProtocolTester, gem5::GarnetSyntheticTraffic, gem5::RubyDirectedTester, gem5::TimingSimpleCPU, gem5::AtomicSimpleCPU, gem5::branch_prediction::TAGEBase, gem5::branch_prediction::StatisticalCorrector, gem5::branch_prediction::MultiperspectivePerceptronTAGE, gem5::branch_prediction::MultiperspectivePerceptron, gem5::branch_prediction::LTAGE, gem5::branch_prediction::LoopPredictor, gem5::o3::CPU, gem5::MinorCPU, gem5::BaseKvmCPU, gem5::CheckerCPU, gem5::BaseCPU, gem5::X86KvmCPU, gem5::X86ISA::Interrupts, gem5::BaseMMU, gem5::ArmISA::MMU, gem5::OutgoingRequestBridge, gem5::SerialLink, gem5::ruby::RubyPortProxy, gem5::ruby::WireBuffer, gem5::ruby::DirectoryMemory, gem5::ruby::CacheMemory, gem5::ruby::AbstractController, gem5::ruby::Switch, gem5::ruby::SimpleNetwork, gem5::ruby::garnet::Router, gem5::ruby::garnet::GarnetNetwork, gem5::ruby::garnet::GarnetExtLink, gem5::ruby::garnet::GarnetIntLink, gem5::ruby::BasicRouter, gem5::ruby::BasicLink, gem5::CoherentXBar, gem5::Wavefront, gem5::Shader, gem5::EtherDump, gem5::TraceCPU, and gem5::SimPoint.
Definition at line 76 of file sim_object.cc.
Referenced by gem5::CoherentXBar::init(), gem5::ruby::garnet::GarnetNetwork::init(), gem5::ruby::SimpleNetwork::init(), gem5::branch_prediction::LTAGE::init(), gem5::BaseTrafficGen::init(), gem5::memory::CfiMemory::init(), gem5::memory::DRAMInterface::init(), gem5::memory::DRAMSim2::init(), gem5::memory::DRAMsim3::init(), gem5::memory::NVMInterface::init(), gem5::memory::qos::MemSinkCtrl::init(), gem5::memory::SimpleMemory::init(), gem5::CxxConfigManager::instantiate(), and gem5::BaseTags::BaseTagStats::regStats().
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Invalidate the contents of memory buffers.
When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.
@warn This does not cause any dirty state to be written back to memory.
Reimplemented in gem5::BaseCache, and gem5::BaseTLB.
Definition at line 313 of file sim_object.hh.
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Write back dirty buffers to memory using functional writes.
After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.
Reimplemented in gem5::ruby::RubySystem, gem5::BaseCache, and gem5::MinorCPU.
Definition at line 298 of file sim_object.hh.
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Definition at line 176 of file sim_object.hh.
References gem5::SimObject::_params.
Referenced by gem5::ruby::Switch::addOutPort(), gem5::ArmProcess::ArmProcess(), gem5::branch_prediction::BPredUnit::BPredUnit(), gem5::StubWorkload::byteOrder(), gem5::ArmISA::ISA::clear(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::VirtIO9PSocket::connectSocket(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::Iris::CPU< TC >::CPU(), gem5::GenericTimer::createTimers(), gem5::ArmISA::Decoder::Decoder(), gem5::SMMUv3DeviceInterface::drain(), gem5::ArmISA::TableWalker::drainResume(), gem5::pseudo_inst::dumpresetstats(), gem5::pseudo_inst::dumpstats(), gem5::MaltaIO::frequency(), gem5::ArmPPIGen::get(), gem5::StubWorkload::getEntry(), gem5::replacement_policy::Dueling::getVictim(), gem5::IdeController::IdeController(), gem5::ruby::AbstractController::init(), gem5::BaseCPU::init(), gem5::MinorCPU::init(), gem5::branch_prediction::MultiperspectivePerceptron::init(), gem5::CpuLocalTimer::init(), gem5::fastmodel::CortexA76::initState(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsWorkload::initState(), gem5::ArmISA::FsLinux::initState(), gem5::RiscvISA::FsLinux::initState(), gem5::memory::AbstractMemory::initState(), gem5::KernelWorkload::initState(), gem5::Iob::Iob(), gem5::memory::AbstractMemory::isNull(), gem5::KernelWorkload::KernelWorkload(), gem5::KvmVM::KvmVM(), gem5::LdsState::LdsState(), gem5::pseudo_inst::loadsymbol(), gem5::pseudo_inst::m5checkpoint(), gem5::ruby::SimpleNetwork::makeExtOutLink(), gem5::MinorCPU::MinorCPU(), gem5::MipsProcess::MipsProcess(), gem5::CommMonitor::MonitorStats::MonitorStats(), gem5::ruby::Network::Network(), gem5::RawDiskImage::notifyFork(), gem5::CowDiskImage::notifyFork(), gem5::PortTerminator::PortTerminator(), gem5::PowerProcess::PowerProcess(), gem5::Process::Process(), gem5::AmbaFake::read(), gem5::IsaFake::read(), gem5::RealViewCtrl::read(), gem5::NSGigE::read(), gem5::pseudo_inst::readfile(), gem5::ruby::RubySystem::registerRequestorIDs(), gem5::BaseMemProbe::regProbeListeners(), gem5::sinic::Device::reset(), gem5::pseudo_inst::resetstats(), gem5::BaseKvmCPU::restartEqThread(), gem5::RiscvProcess::RiscvProcess(), gem5::ruby::WeightBased::route(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexA76::setCluster(), gem5::fastmodel::CortexR52::setCluster(), gem5::ArmISA::FsWorkload::setSystem(), gem5::ArmISA::SEWorkload::setSystem(), gem5::MipsISA::SEWorkload::setSystem(), gem5::PowerISA::SEWorkload::setSystem(), gem5::RiscvISA::BareMetal::setSystem(), gem5::RiscvISA::FsLinux::setSystem(), gem5::RiscvISA::SEWorkload::setSystem(), gem5::SparcISA::FsWorkload::setSystem(), gem5::SparcISA::SEWorkload::setSystem(), gem5::X86ISA::FsWorkload::setSystem(), gem5::X86ISA::EmuLinux::setSystem(), gem5::CheckerCPU::setSystem(), gem5::ArmISA::PMU::setThreadContext(), gem5::SimpleCache::SimpleCache(), gem5::branch_prediction::SimpleIndirectPredictor::SimpleIndirectPredictor(), gem5::SMMUv3::SMMUv3(), gem5::SparcProcess::SparcProcess(), gem5::StackDistProbe::StackDistProbeStats::StackDistProbeStats(), gem5::VirtIO9PDiod::startDiod(), gem5::BaseArmKvmCPU::startup(), gem5::ArmISA::FsLinux::startup(), gem5::BaseCPU::startup(), gem5::BaseKvmCPU::startup(), gem5::Root::startup(), gem5::System::System(), gem5::ruby::Topology::Topology(), gem5::Process::tryLoaders(), gem5::VirtIO9PBase::VirtIO9PBase(), gem5::pseudo_inst::workbegin(), gem5::pseudo_inst::workend(), gem5::AmbaFake::write(), gem5::IsaFake::write(), gem5::IGbE::write(), gem5::X86ISA::ACPI::RSDP::write(), and gem5::X86ISA::ACPI::SysDescTable::writeBuf().
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Register probe listeners for this object.
No probe listeners by default, so do nothing in base.
Reimplemented in gem5::BaseMemProbe, gem5::prefetch::Base, gem5::compression::FrequentValues, gem5::o3::SimpleTrace, gem5::ArmISA::PMU, gem5::SimPoint, and gem5::o3::ElasticTrace.
Definition at line 115 of file sim_object.cc.
Referenced by gem5::CxxConfigManager::instantiate().
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Register probe points for this object.
No probe points by default, so do nothing in base.
Reimplemented in gem5::CommMonitor, gem5::BaseCache, gem5::AtomicSimpleCPU, gem5::branch_prediction::BPredUnit, gem5::o3::CPU, gem5::BaseCPU, gem5::ArmISA::TLB, and gem5::PowerModel.
Definition at line 107 of file sim_object.cc.
Referenced by gem5::CxxConfigManager::instantiate().
| gem5::SimObject::SimObject | ( | const Params & | p | ) |
Definition at line 58 of file sim_object.cc.
References gem5::SimObject::probeManager, and gem5::SimObject::simObjectList.
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startup() is the final initialization call before simulation.
All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.
Reimplemented in sc_gem5::Kernel, gem5::Workload, gem5::VoltageDomain, gem5::Root, gem5::PowerDomain, gem5::ThermalModel, gem5::MathExprPowerModel, gem5::SrcClockDomain, gem5::ruby::RubySystem, gem5::MemTraceProbe, gem5::memory::NVMInterface, gem5::memory::MemCtrl, gem5::memory::HBMCtrl, gem5::memory::DRAMsim3, gem5::memory::DRAMSim2, gem5::memory::DRAMInterface, gem5::CommMonitor, gem5::prefetch::AccessMapPatternMatching, gem5::X86ISA::I8254, gem5::X86ISA::Cmos, gem5::RiscvRTC, gem5::DistEtherLink, gem5::MaltaIO, gem5::RealViewOsc, gem5::FVPBasePwrCtrl, gem5::EnergyCtrl, gem5::GUPSGen, gem5::o3::CPU, gem5::MinorCPU, gem5::BaseKvmCPU, gem5::BaseCPU, gem5::X86KvmCPU, gem5::ArmISA::FsLinux, gem5::BaseArmKvmCPU, gem5::ArmV8KvmCPU, gem5::ArmISA::ISA, gem5::HelloObject, gem5::VirtIO9PSocket, gem5::VirtIO9PDiod, and gem5::ArmKvmCPU.
Definition at line 99 of file sim_object.cc.
Referenced by gem5::memory::HeteroMemCtrl::drainResume(), gem5::memory::MemCtrl::drainResume(), gem5::CxxConfigManager::startup(), gem5::ArmISA::ISA::startup(), gem5::FVPBasePwrCtrl::startup(), and gem5::Workload::startup().
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Cached copy of the object parameters.
Definition at line 167 of file sim_object.hh.
Referenced by gem5::PMAChecker::params(), gem5::BaseGic::params(), gem5::PlicIntDevice::params(), and gem5::SimObject::params().