gem5 v24.0.0.0
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gem5::PowerISA::IntLogicOp Member List

This is the complete list of members for gem5::PowerISA::IntLogicOp, including all inherited members.

_destRegIdxPtrgem5::StaticInstprivate
_numDestRegsgem5::StaticInstprotected
_numSrcRegsgem5::StaticInstprotected
_numTypedDestRegsgem5::StaticInstprotected
_opClassgem5::StaticInstprotected
_sizegem5::StaticInstprotected
_srcRegIdxPtrgem5::StaticInstprivate
advancePC(PCStateBase &pc_state) const overridegem5::PowerISA::PowerStaticInstinlineprotectedvirtual
advancePC(ThreadContext *tc) const overridegem5::PowerISA::PowerStaticInstinlineprotectedvirtual
asBytes(void *buf, size_t max_size) overridegem5::PowerISA::PowerStaticInstinlineprotectedvirtual
branchTarget(const PCStateBase &pc) constgem5::StaticInstvirtual
branchTarget(ThreadContext *tc) constgem5::StaticInstvirtual
buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const overridegem5::PowerISA::PowerStaticInstinlineprotectedvirtual
cachedDisassemblygem5::StaticInstmutableprotected
completeAcc(Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) constgem5::StaticInstinlinevirtual
countgem5::RefCountedmutableprivate
decref() constgem5::RefCountedinline
destRegIdx(int i) constgem5::StaticInstinline
disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) constgem5::StaticInstvirtual
execute(ExecContext *xc, trace::InstRecord *traceData) const =0gem5::StaticInstpure virtual
fetchMicroop(MicroPC upc) constgem5::StaticInstvirtual
findLeadingZeros(uint32_t rs) constgem5::PowerISA::IntLogicOpinlineprotected
findLeadingZeros(uint64_t rs) constgem5::PowerISA::IntLogicOpinlineprotected
findTrailingZeros(uint32_t rs) constgem5::PowerISA::IntLogicOpinlineprotected
findTrailingZeros(uint64_t rs) constgem5::PowerISA::IntLogicOpinlineprotected
flagsgem5::StaticInstprotected
generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const overridegem5::PowerISA::IntLogicOpprotectedvirtual
getEMI() constgem5::StaticInstinlinevirtual
getName()gem5::StaticInstinline
incref() constgem5::RefCountedinline
initiateAcc(ExecContext *xc, trace::InstRecord *traceData) constgem5::StaticInstinlinevirtual
insertCRField(uint32_t cr, uint32_t bf, uint32_t value) constgem5::PowerISA::PowerStaticInstinlineprotected
IntLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)gem5::PowerISA::IntLogicOpinlineprotected
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass)gem5::PowerISA::IntOpinlineprotected
isAtomic() constgem5::StaticInstinline
isCall() constgem5::StaticInstinline
isCondCtrl() constgem5::StaticInstinline
isControl() constgem5::StaticInstinline
isDataPrefetch() constgem5::StaticInstinline
isDelayedCommit() constgem5::StaticInstinline
isDirectCtrl() constgem5::StaticInstinline
isFirstMicroop() constgem5::StaticInstinline
isFloating() constgem5::StaticInstinline
isFullMemBarrier() constgem5::StaticInstinline
isHtmCancel() constgem5::StaticInstinline
isHtmCmd() constgem5::StaticInstinline
isHtmStart() constgem5::StaticInstinline
isHtmStop() constgem5::StaticInstinline
isIndirectCtrl() constgem5::StaticInstinline
isInstPrefetch() constgem5::StaticInstinline
isInteger() constgem5::StaticInstinline
isInvalid() constgem5::StaticInstinline
isLastMicroop() constgem5::StaticInstinline
isLoad() constgem5::StaticInstinline
isMacroop() constgem5::StaticInstinline
isMatrix() constgem5::StaticInstinline
isMemRef() constgem5::StaticInstinline
isMicroop() constgem5::StaticInstinline
isNonSpeculative() constgem5::StaticInstinline
isNop() constgem5::StaticInstinline
isPrefetch() constgem5::StaticInstinline
isPseudo() constgem5::StaticInstinline
isQuiesce() constgem5::StaticInstinline
isReadBarrier() constgem5::StaticInstinline
isReturn() constgem5::StaticInstinline
isSerializeAfter() constgem5::StaticInstinline
isSerializeBefore() constgem5::StaticInstinline
isSerializing() constgem5::StaticInstinline
isSquashAfter() constgem5::StaticInstinline
isStore() constgem5::StaticInstinline
isStoreConditional() constgem5::StaticInstinline
isSyscall() constgem5::StaticInstinline
isUncondCtrl() constgem5::StaticInstinline
isUnverifiable() constgem5::StaticInstinline
isVector() constgem5::StaticInstinline
isWriteBarrier() constgem5::StaticInstinline
machInstgem5::PowerISA::PowerStaticInstprotected
makeCRFieldSigned(int64_t a, int64_t b, bool so) constgem5::PowerISA::IntOpinlineprotected
makeCRFieldUnsigned(uint64_t a, uint64_t b, bool so) constgem5::PowerISA::IntOpinlineprotected
mnemonicgem5::StaticInstprotected
nullStaticInstPtrgem5::StaticInststatic
numDestRegs() constgem5::StaticInstinline
numDestRegs(RegClassType type) constgem5::StaticInstinline
numSrcRegs() constgem5::StaticInstinline
oegem5::PowerISA::IntOpprotected
opClass() constgem5::StaticInstinline
operator=(const RefCounted &)gem5::RefCountedprivate
PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)gem5::PowerISA::PowerStaticInstinlineprotected
printFlags(std::ostream &outs, const std::string &separator) constgem5::StaticInst
printReg(std::ostream &os, RegId reg) constgem5::PowerISA::PowerStaticInstprotected
rcgem5::PowerISA::IntOpprotected
RefCounted(const RefCounted &)gem5::RefCountedprivate
RefCounted()gem5::RefCountedinline
RegIdArrayPtr typedefgem5::StaticInst
setDelayedCommit()gem5::StaticInstinline
setDestRegIdx(int i, const RegId &val)gem5::StaticInstinline
setFirstMicroop()gem5::StaticInstinline
setFlag(Flags f)gem5::StaticInstinline
setLastMicroop()gem5::StaticInstinline
setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)gem5::StaticInstinlineprotected
setSrcRegIdx(int i, const RegId &val)gem5::StaticInstinline
shgem5::PowerISA::IntOpprotected
simpleAsBytes(void *buf, size_t max_size, const T &t)gem5::StaticInstinlineprotected
size() constgem5::StaticInstinline
size(size_t newSize)gem5::StaticInstinlinevirtual
srcRegIdx(int i) constgem5::StaticInstinline
StaticInst(const char *_mnemonic, OpClass op_class)gem5::StaticInstinlineprotected
~RefCounted()gem5::RefCountedinlinevirtual
~StaticInst()gem5::StaticInstinlinevirtual
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