|
gem5 v24.0.0.0
|
This is the complete list of members for gem5::RegRegRegOp, including all inherited members.
| _destRegIdxPtr | gem5::StaticInst | private |
| _numDestRegs | gem5::StaticInst | protected |
| _numSrcRegs | gem5::StaticInst | protected |
| _numTypedDestRegs | gem5::StaticInst | protected |
| _opClass | gem5::StaticInst | protected |
| _size | gem5::StaticInst | protected |
| _srcRegIdxPtr | gem5::StaticInst | private |
| aarch64 | gem5::ArmISA::ArmStaticInst | protected |
| activateBreakpoint(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| advancePC(PCStateBase &pcState) const override | gem5::ArmISA::ArmStaticInst | inlineprotectedvirtual |
| advancePC(ThreadContext *tc) const override | gem5::ArmISA::ArmStaticInst | inlineprotectedvirtual |
| advSIMDFPAccessTrap64(ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| annotateFault(ArmFault *fault) | gem5::ArmISA::ArmStaticInst | inlinevirtual |
| ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::ArmISA::ArmStaticInst | inlineprotected |
| asBytes(void *buf, size_t max_size) override | gem5::ArmISA::ArmStaticInst | inlinevirtual |
| branchTarget(const PCStateBase &pc) const | gem5::StaticInst | virtual |
| branchTarget(ThreadContext *tc) const | gem5::StaticInst | virtual |
| buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override | gem5::ArmISA::ArmStaticInst | inlineprotectedvirtual |
| cachedDisassembly | gem5::StaticInst | mutableprotected |
| checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const | gem5::ArmISA::ArmStaticInst | protected |
| checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSmeAccess(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSmeEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| checkSveSmeEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | gem5::ArmISA::ArmStaticInst | protected |
| completeAcc(Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const | gem5::StaticInst | inlinevirtual |
| condCode | gem5::ArmISA::PredOp | protected |
| count | gem5::RefCounted | mutableprivate |
| cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| decref() const | gem5::RefCounted | inline |
| dest | gem5::RegRegRegOp | protected |
| destRegIdx(int i) const | gem5::StaticInst | inline |
| disabledFault() const | gem5::ArmISA::ArmStaticInst | inlineprotected |
| disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const | gem5::StaticInst | virtual |
| encoding() const | gem5::ArmISA::ArmStaticInst | inline |
| execute(ExecContext *xc, trace::InstRecord *traceData) const =0 | gem5::StaticInst | pure virtual |
| extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const | gem5::ArmISA::ArmStaticInst | protected |
| fetchMicroop(MicroPC upc) const | gem5::StaticInst | virtual |
| flags | gem5::StaticInst | protected |
| generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const | gem5::ArmISA::ArmStaticInst | protected |
| generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override | gem5::RegRegRegOp | protectedvirtual |
| getCurSmeVecLen(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getCurSmeVecLenInBits(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | static |
| getCurSmeVecLenInQWords(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getCurSveVecLen(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getCurSveVecLenInBits(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | static |
| getCurSveVecLenInQWords(ThreadContext *tc) | gem5::ArmISA::ArmStaticInst | inlinestatic |
| getEMI() const override | gem5::ArmISA::ArmStaticInst | inlineprotectedvirtual |
| getIntWidth() const | gem5::ArmISA::ArmStaticInst | inline |
| getName() | gem5::StaticInst | inline |
| getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const | gem5::ArmISA::ArmStaticInst | protected |
| incref() const | gem5::RefCounted | inline |
| initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const | gem5::StaticInst | inlinevirtual |
| instSize() const | gem5::ArmISA::ArmStaticInst | inline |
| intWidth | gem5::ArmISA::ArmStaticInst | protected |
| isAtomic() const | gem5::StaticInst | inline |
| isCall() const | gem5::StaticInst | inline |
| isCondCtrl() const | gem5::StaticInst | inline |
| isControl() const | gem5::StaticInst | inline |
| isDataPrefetch() const | gem5::StaticInst | inline |
| isDelayedCommit() const | gem5::StaticInst | inline |
| isDirectCtrl() const | gem5::StaticInst | inline |
| isFirstMicroop() const | gem5::StaticInst | inline |
| isFloating() const | gem5::StaticInst | inline |
| isFullMemBarrier() const | gem5::StaticInst | inline |
| isHtmCancel() const | gem5::StaticInst | inline |
| isHtmCmd() const | gem5::StaticInst | inline |
| isHtmStart() const | gem5::StaticInst | inline |
| isHtmStop() const | gem5::StaticInst | inline |
| isIndirectCtrl() const | gem5::StaticInst | inline |
| isInstPrefetch() const | gem5::StaticInst | inline |
| isInteger() const | gem5::StaticInst | inline |
| isInvalid() const | gem5::StaticInst | inline |
| isLastMicroop() const | gem5::StaticInst | inline |
| isLoad() const | gem5::StaticInst | inline |
| isMacroop() const | gem5::StaticInst | inline |
| isMatrix() const | gem5::StaticInst | inline |
| isMemRef() const | gem5::StaticInst | inline |
| isMicroop() const | gem5::StaticInst | inline |
| isNonSpeculative() const | gem5::StaticInst | inline |
| isNop() const | gem5::StaticInst | inline |
| isPrefetch() const | gem5::StaticInst | inline |
| isPseudo() const | gem5::StaticInst | inline |
| isQuiesce() const | gem5::StaticInst | inline |
| isReadBarrier() const | gem5::StaticInst | inline |
| isReturn() const | gem5::StaticInst | inline |
| isSerializeAfter() const | gem5::StaticInst | inline |
| isSerializeBefore() const | gem5::StaticInst | inline |
| isSerializing() const | gem5::StaticInst | inline |
| isSquashAfter() const | gem5::StaticInst | inline |
| isStore() const | gem5::StaticInst | inline |
| isStoreConditional() const | gem5::StaticInst | inline |
| isSyscall() const | gem5::StaticInst | inline |
| isUncondCtrl() const | gem5::StaticInst | inline |
| isUnverifiable() const | gem5::StaticInst | inline |
| isVector() const | gem5::StaticInst | inline |
| isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const | gem5::ArmISA::ArmStaticInst | inlineprotected |
| isWriteBarrier() const | gem5::StaticInst | inline |
| machInst | gem5::ArmISA::ArmStaticInst | protected |
| mnemonic | gem5::StaticInst | protected |
| nullStaticInstPtr | gem5::StaticInst | static |
| numDestRegs() const | gem5::StaticInst | inline |
| numDestRegs(RegClassType type) const | gem5::StaticInst | inline |
| numSrcRegs() const | gem5::StaticInst | inline |
| op1 | gem5::RegRegRegOp | protected |
| op2 | gem5::RegRegRegOp | protected |
| opClass() const | gem5::StaticInst | inline |
| operator=(const RefCounted &) | gem5::RefCounted | private |
| PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::ArmISA::PredOp | inlineprotected |
| printCCReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const | gem5::ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm) const | gem5::ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, RegIndex rd, RegIndex rn, RegIndex rm, RegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const | gem5::ArmISA::ArmStaticInst | protected |
| printExtendOperand(bool firstOperand, std::ostream &os, RegIndex rm, ArmExtendType type, int64_t shiftAmt) const | gem5::ArmISA::ArmStaticInst | protected |
| printFlags(std::ostream &outs, const std::string &separator) const | gem5::StaticInst | |
| printFloatReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const | gem5::ArmISA::ArmStaticInst | protected |
| printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const | gem5::ArmISA::ArmStaticInst | protected |
| printMiscReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const | gem5::ArmISA::ArmStaticInst | protected |
| printPFflags(std::ostream &os, int flag) const | gem5::ArmISA::ArmStaticInst | protected |
| printShiftOperand(std::ostream &os, RegIndex rm, bool immShift, uint32_t shiftAmt, RegIndex rs, ArmShiftType type) const | gem5::ArmISA::ArmStaticInst | protected |
| printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const | gem5::ArmISA::ArmStaticInst | protected |
| printVecPredReg(std::ostream &os, RegIndex reg_idx) const | gem5::ArmISA::ArmStaticInst | protected |
| printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const | gem5::ArmISA::ArmStaticInst | protected |
| readPC(ExecContext *xc) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| RefCounted(const RefCounted &) | gem5::RefCounted | private |
| RefCounted() | gem5::RefCounted | inline |
| RegIdArrayPtr typedef | gem5::StaticInst | |
| RegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, RegIndex _op2) | gem5::RegRegRegOp | inlineprotected |
| satInt(int32_t &res, int64_t op, int width) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setAIWNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setDelayedCommit() | gem5::StaticInst | inline |
| setDestRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| setFirstMicroop() | gem5::StaticInst | inline |
| setFlag(Flags f) | gem5::StaticInst | inline |
| setIWNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setLastMicroop() | gem5::StaticInst | inline |
| setNextPC(ExecContext *xc, Addr val) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest) | gem5::StaticInst | inlineprotected |
| setSrcRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | gem5::ArmISA::ArmStaticInst | protected |
| shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const | gem5::ArmISA::ArmStaticInst | protected |
| simpleAsBytes(void *buf, size_t max_size, const T &t) | gem5::StaticInst | inlineprotected |
| size() const | gem5::StaticInst | inline |
| size(size_t newSize) | gem5::StaticInst | inlinevirtual |
| smeAccessTrap(ExceptionLevel el, uint32_t iss=0) const | gem5::ArmISA::ArmStaticInst | protected |
| softwareBreakpoint32(ExecContext *xc, uint16_t imm) const | gem5::ArmISA::ArmStaticInst | protected |
| spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| srcRegIdx(int i) const | gem5::StaticInst | inline |
| StaticInst(const char *_mnemonic, OpClass op_class) | gem5::StaticInst | inlineprotected |
| sveAccessTrap(ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const | gem5::ArmISA::ArmStaticInst | protected |
| undefined(bool disabled=false) const | gem5::ArmISA::ArmStaticInst | inline |
| undefinedFault32(ThreadContext *tc, ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| undefinedFault64(ThreadContext *tc, ExceptionLevel el) const | gem5::ArmISA::ArmStaticInst | protected |
| uSatInt(int32_t &res, int64_t op, int width) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) | gem5::ArmISA::ArmStaticInst | inlineprotectedstatic |
| ~RefCounted() | gem5::RefCounted | inlinevirtual |
| ~StaticInst() | gem5::StaticInst | inlinevirtual |