gem5 v24.0.0.0
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data_gen.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 data_gen.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38#include "define.h"
39
40/******************************************************************************/
41/*************************** data_gen Function **********************/
42/******************************************************************************/
43
44SC_MODULE( DATA_GEN )
45{
46 SC_HAS_PROCESS( DATA_GEN );
47
48 sc_in_clk clk;
49
50 /*** Input and Output Ports ***/
51 const sc_signal<bool>& ready;
53 sc_signal<int>& addr;
54
55 /*** Constructor ***/
56 DATA_GEN ( sc_module_name NAME,
57 sc_clock& TICK_N,
58 const sc_signal<bool>& READY,
60 sc_signal<int>& ADDR )
61
62 :
63 ready (READY),
64 data (DATA), // 8 bits
65 addr (ADDR)
66
67 {
68 clk (TICK_N);
69 SC_CTHREAD( entry, clk.neg() );
70 }
71
72 /*** Call to Process Functionality ***/
73 void entry();
74
75};
76
77void
78DATA_GEN::entry()
79{
80
81 while(true) {
82
83// WAIT FOR POSEDGE OF ready
84
85 at_posedge(ready);
86
87// CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED
88
89 if(addr.read() > LIMIT) { // if(addr > LIMIT)
90 break;
91 }
92
93// WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data
94// INCREMENT addr BY 1
95
96 data.write(mem[addr.read()]); // data = mem[addr]
97 addr.write(addr.read() + 1); // addr = addr + 1
98 }
99
100}
const char data[]
Bitfield< 3 > addr
Definition types.hh:84
void at_posedge(const sc_signal_in_if< bool > &s)
Definition sc_module.cc:784
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
#define SC_MODULE(name)
Definition sc_module.hh:295
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition common.h:43
#define LIMIT
Definition define.h:40
bool_vector8 mem[]
Definition reset_stim.h:43

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