gem5  v22.0.0.1
pagetable.hh
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1 /*
2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_MIPS_PAGETABLE_H__
31 #define __ARCH_MIPS_PAGETABLE_H__
32 
33 #include "base/logging.hh"
34 #include "base/types.hh"
35 #include "sim/serialize.hh"
36 
37 namespace gem5
38 {
39 
40 namespace MipsISA {
41 
42 // ITB/DTB page table entry
43 struct PTE
44 {
47  uint8_t asid;
48 
49  bool G;
50 
51  /* Contents of Entry Lo0 */
52  Addr PFN0; // Physical Frame Number - Even
53  bool D0; // Even entry Dirty Bit
54  bool V0; // Even entry Valid Bit
55  uint8_t C0; // Cache Coherency Bits - Even
56 
57  /* Contents of Entry Lo1 */
58  Addr PFN1; // Physical Frame Number - Odd
59  bool D1; // Odd entry Dirty Bit
60  bool V1; // Odd entry Valid Bit
61  uint8_t C1; // Cache Coherency Bits (3 bits)
62 
63  /*
64  * The next few variables are put in as optimizations to reduce
65  * TLB lookup overheads. For a given Mask, what is the address shift
66  * amount, and what is the OffsetMask
67  */
70 
71  bool Valid() { return (V0 | V1); };
72  void serialize(CheckpointOut &cp) const;
73  void unserialize(CheckpointIn &cp);
74 };
75 
76 // WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
77 struct TlbEntry
78 {
80  TlbEntry() {}
81  TlbEntry(Addr asn, Addr vaddr, Addr paddr,
82  bool uncacheable, bool read_only)
83  : _pageStart(paddr)
84  {
85  if (uncacheable || read_only)
86  warn("MIPS TlbEntry does not support uncacheable"
87  " or read-only mappings\n");
88  }
89 
91  {
92  return _pageStart;
93  }
94 
95  void
96  updateVaddr(Addr new_vaddr) {}
97 
98  void serialize(CheckpointOut &cp) const
99  {
101  }
102 
104  {
106  }
107 
108 };
109 
110 } // namespace MipsISA
111 } // namespace gem5
112 
113 #endif // __ARCH_MIPS_PAGETABLE_H__
warn
#define warn(...)
Definition: logging.hh:246
gem5::MipsISA::PTE::unserialize
void unserialize(CheckpointIn &cp)
Definition: pagetable.cc:60
serialize.hh
gem5::MipsISA::TlbEntry
Definition: pagetable.hh:77
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::MipsISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp)
Definition: pagetable.hh:103
gem5::MipsISA::PTE::asid
uint8_t asid
Definition: pagetable.hh:47
gem5::MipsISA::TlbEntry::updateVaddr
void updateVaddr(Addr new_vaddr)
Definition: pagetable.hh:96
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MipsISA::TlbEntry::pageStart
Addr pageStart()
Definition: pagetable.hh:90
gem5::MipsISA::PTE::serialize
void serialize(CheckpointOut &cp) const
Definition: pagetable.cc:41
gem5::MipsISA::PTE::D0
bool D0
Definition: pagetable.hh:53
gem5::MipsISA::PTE::C0
uint8_t C0
Definition: pagetable.hh:55
gem5::MipsISA::TlbEntry::TlbEntry
TlbEntry()
Definition: pagetable.hh:80
gem5::MipsISA::PTE::PFN1
Addr PFN1
Definition: pagetable.hh:58
gem5::MipsISA::PTE::V0
bool V0
Definition: pagetable.hh:54
gem5::MipsISA::PTE::Valid
bool Valid()
Definition: pagetable.hh:71
gem5::MipsISA::PTE::C1
uint8_t C1
Definition: pagetable.hh:61
gem5::MipsISA::PTE::G
bool G
Definition: pagetable.hh:49
gem5::MipsISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const
Definition: pagetable.hh:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::MipsISA::PTE::V1
bool V1
Definition: pagetable.hh:60
gem5::MipsISA::PTE::OffsetMask
int OffsetMask
Definition: pagetable.hh:69
gem5::MipsISA::TlbEntry::TlbEntry
TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only)
Definition: pagetable.hh:81
types.hh
gem5::MipsISA::PTE::D1
bool D1
Definition: pagetable.hh:59
gem5::MipsISA::PTE
Definition: pagetable.hh:43
logging.hh
gem5::MipsISA::PTE::PFN0
Addr PFN0
Definition: pagetable.hh:52
gem5::MipsISA::TlbEntry::_pageStart
Addr _pageStart
Definition: pagetable.hh:79
gem5::MipsISA::PTE::AddrShiftAmount
int AddrShiftAmount
Definition: pagetable.hh:68
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::PTE::VPN
Addr VPN
Definition: pagetable.hh:46
gem5::MipsISA::PTE::Mask
Addr Mask
Definition: pagetable.hh:45

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