gem5  v22.0.0.2
types.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
35 #ifndef __BASE_TYPES_HH__
36 #define __BASE_TYPES_HH__
37 
38 #include <inttypes.h>
39 
40 #include <cassert>
41 #include <limits>
42 #include <memory>
43 #include <ostream>
44 #include <stdexcept>
45 
46 namespace gem5
47 {
48 
53 typedef int64_t Counter;
54 
58 typedef uint64_t Tick;
59 
60 const Tick MaxTick = 0xffffffffffffffffULL;
61 
78 class Cycles
79 {
80 
81  private:
82 
84  uint64_t c;
85 
86  public:
87 
89  explicit constexpr Cycles(uint64_t _c) : c(_c) { }
90 
92  Cycles() : c(0) { }
93 
95  constexpr operator uint64_t() const { return c; }
96 
98  Cycles& operator++() { ++c; return *this; }
99 
101  Cycles& operator--() { assert(c != 0); --c; return *this; }
102 
104  Cycles& operator+=(const Cycles& cc) { c += cc.c; return *this; }
105 
107  constexpr bool
108  operator>(const Cycles& cc) const
109  {
110  return c > cc.c;
111  }
112 
113  constexpr Cycles
114  operator+(const Cycles& b) const
115  {
116  return Cycles(c + b.c);
117  }
118 
119  constexpr Cycles
120  operator-(const Cycles& b) const
121  {
122  return c >= b.c ? Cycles(c - b.c) :
123  throw std::invalid_argument("RHS cycle value larger than LHS");
124  }
125 
126  constexpr Cycles
127  operator <<(const int32_t shift) const
128  {
129  return Cycles(c << shift);
130  }
131 
132  constexpr Cycles
133  operator >>(const int32_t shift) const
134  {
135  return Cycles(c >> shift);
136  }
137 
138  friend std::ostream& operator<<(std::ostream &out, const Cycles & cycles);
139 };
140 
147 typedef uint64_t Addr;
148 
149 typedef uint16_t MicroPC;
150 
151 static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1);
152 
153 static inline MicroPC
155 {
156  return upc | MicroPCRomBit;
157 }
158 
159 static inline MicroPC
161 {
162  return upc & ~MicroPCRomBit;
163 }
164 
165 static inline bool
167 {
168  return MicroPCRomBit & upc;
169 }
170 
171 const Addr MaxAddr = (Addr)-1;
172 
173 using RegVal = uint64_t;
174 
175 // Logical register index type.
176 using RegIndex = uint16_t;
177 
178 static inline uint32_t
180 {
181  union
182  {
183  float f;
184  uint32_t i;
185  } u;
186  u.f = val;
187  return u.i;
188 }
189 
190 static inline uint64_t
192 {
193  union
194  {
195  double f;
196  uint64_t i;
197  } u;
198  u.f = val;
199  return u.i;
200 }
201 
202 static inline uint64_t floatToBits(double val) { return floatToBits64(val); }
203 static inline uint32_t floatToBits(float val) { return floatToBits32(val); }
204 
205 static inline float
207 {
208  union
209  {
210  float f;
211  uint32_t i;
212  } u;
213  u.i = val;
214  return u.f;
215 }
216 
217 static inline double
219 {
220  union
221  {
222  double f;
223  uint64_t i;
224  } u;
225  u.i = val;
226  return u.f;
227 }
228 
229 static inline double bitsToFloat(uint64_t val) { return bitsToFloat64(val); }
230 static inline float bitsToFloat(uint32_t val) { return bitsToFloat32(val); }
231 
235 typedef int16_t ThreadID;
237 
239 typedef int ContextID;
241 
245 typedef int16_t PortID;
247 
248 class FaultBase;
249 typedef std::shared_ptr<FaultBase> Fault;
250 
251 // Rather than creating a shared_ptr instance and assigning it nullptr,
252 // we just create an alias.
253 constexpr decltype(nullptr) NoFault = nullptr;
254 
255 } // namespace gem5
256 
257 #endif // __BASE_TYPES_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::VegaISA::f
Bitfield< 56 > f
Definition: pagetable.hh:53
gem5::bitsToFloat32
static float bitsToFloat32(uint32_t val)
Definition: types.hh:206
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:53
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::floatToBits32
static uint32_t floatToBits32(float val)
Definition: types.hh:179
gem5::normalMicroPC
static MicroPC normalMicroPC(MicroPC upc)
Definition: types.hh:160
gem5::isRomMicroPC
static bool isRomMicroPC(MicroPC upc)
Definition: types.hh:166
gem5::Cycles::operator--
Cycles & operator--()
Prefix decrement operator.
Definition: types.hh:101
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:240
gem5::bitsToFloat64
static double bitsToFloat64(uint64_t val)
Definition: types.hh:218
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::Cycles::operator++
Cycles & operator++()
Prefix increment operator.
Definition: types.hh:98
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Cycles::operator<<
constexpr Cycles operator<<(const int32_t shift) const
Definition: types.hh:127
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Cycles::operator>
constexpr bool operator>(const Cycles &cc) const
Greater than comparison used for > Cycles(0).
Definition: types.hh:108
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:117
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::floatToBits
static uint64_t floatToBits(double val)
Definition: types.hh:202
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::Cycles::Cycles
Cycles()
Default constructor for parameter classes.
Definition: types.hh:92
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Cycles::c
uint64_t c
Member holding the actual value.
Definition: types.hh:84
gem5::bitsToFloat
static double bitsToFloat(uint64_t val)
Definition: types.hh:229
gem5::InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:236
gem5::Cycles::operator-
constexpr Cycles operator-(const Cycles &b) const
Definition: types.hh:120
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Cycles::Cycles
constexpr Cycles(uint64_t _c)
Explicit constructor assigning a value.
Definition: types.hh:89
gem5::Cycles::operator>>
constexpr Cycles operator>>(const int32_t shift) const
Definition: types.hh:133
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:353
gem5::floatToBits64
static uint64_t floatToBits64(double val)
Definition: types.hh:191
gem5::FaultBase
Definition: translation_gen.test.cc:49
gem5::Cycles::operator+=
Cycles & operator+=(const Cycles &cc)
In-place addition of cycles.
Definition: types.hh:104
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::romMicroPC
static MicroPC romMicroPC(MicroPC upc)
Definition: types.hh:154
gem5::MicroPCRomBit
static const MicroPC MicroPCRomBit
Definition: types.hh:151
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Cycles::operator+
constexpr Cycles operator+(const Cycles &b) const
Definition: types.hh:114
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235

Generated on Thu Jul 28 2022 13:32:25 for gem5 by doxygen 1.8.17