gem5  v22.1.0.0
pra_constants.hh
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28 
29 #ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__
30 #define __ARCH_MIPS_PRA_CONSTANTS_HH__
31 
32 #include "arch/mips/types.hh"
33 #include "base/bitunion.hh"
34 
35 namespace gem5
36 {
37 
38 namespace MipsISA
39 {
40 
41 BitUnion32(IndexReg)
42  Bitfield<31> p;
43  // Need to figure out how to put in the TLB specific bits here
44  // For now, we assume that the entire length is used by the index
45  // field In reality, Index_HI = N-1, where
46  // N = Ceiling(log2(TLB Entries))
47  Bitfield<30, 0> index;
48 EndBitUnion(IndexReg)
49 
50 BitUnion32(RandomReg)
51  // This has a problem similar to the IndexReg index field. We'll keep
52  // both consistent at 30 for now
53  Bitfield<30, 0> random;
54 EndBitUnion(RandomReg)
55 
56 BitUnion64(EntryLoReg)
57  Bitfield<63, 30> fill;
58  Bitfield<29, 6> pfn; // Page frame number
59  Bitfield<5, 3> c; // Coherency attribute
60  Bitfield<2> d; // Dirty Bit
61  Bitfield<1> v; // Valid Bit
62  Bitfield<0> g; // Global Bit
63 EndBitUnion(EntryLoReg)
64 
65 BitUnion64(ContextReg)
66  Bitfield<63, 23> pteBase;
67  Bitfield<22, 4> badVPN2;
68  // Bits 3-0 are 0
69 EndBitUnion(ContextReg)
70 
71 BitUnion32(PageMaskReg)
72  // Bits 31-29 are 0
73  Bitfield<28, 13> mask;
74  Bitfield<12, 11> maskx;
75  // Bits 10-0 are zero
76 EndBitUnion(PageMaskReg)
77 
78 BitUnion32(PageGrainReg)
79  Bitfield<31, 30> aseUp;
80  Bitfield<29> elpa;
81  Bitfield<28> esp;
82  // Bits 27-13 are zeros
83  Bitfield<12, 8> aseDn;
84  // Bits 7-0 are zeros
85 EndBitUnion(PageGrainReg)
86 
87 BitUnion32(WiredReg)
88  // See note on Index register above
89  Bitfield<30, 0> wired;
90 EndBitUnion(WiredReg)
91 
92 BitUnion32(HWREnaReg)
93  Bitfield<31, 30> impl;
94  Bitfield<3, 0> mask;
95 EndBitUnion(HWREnaReg)
96 
97 BitUnion64(EntryHiReg)
98  Bitfield<63, 62> r;
99  Bitfield<61, 40> fill;
100  Bitfield<39, 13> vpn2;
101  Bitfield<12, 11> vpn2x;
102  Bitfield<7, 0> asid;
103 EndBitUnion(EntryHiReg)
104 
105 BitUnion32(StatusReg)
106  SubBitUnion(cu, 31, 28)
107  Bitfield<31> cu3;
108  Bitfield<30> cu2;
109  Bitfield<29> cu1;
110  Bitfield<28> cu0;
112  Bitfield<27> rp;
113  Bitfield<26> fr;
114  Bitfield<25> re;
115  Bitfield<24> mx;
116  Bitfield<23> px;
117  Bitfield<22> bev;
118  Bitfield<21> ts;
119  Bitfield<20> sr;
120  Bitfield<19> nmi;
121  // Bit 18 is zero
122  Bitfield<17, 16> impl;
123  Bitfield<15, 10> ipl;
124  SubBitUnion(im, 15, 8)
125  Bitfield<15> im7;
126  Bitfield<14> im6;
127  Bitfield<13> im5;
128  Bitfield<12> im4;
129  Bitfield<11> im3;
130  Bitfield<10> im2;
131  Bitfield<9> im1;
132  Bitfield<8> im0;
134  Bitfield<7> kx;
135  Bitfield<6> sx;
136  Bitfield<5> ux;
137  Bitfield<4, 3> ksu;
138  Bitfield<4> um;
139  Bitfield<3> r0;
140  Bitfield<2> erl;
141  Bitfield<1> exl;
142  Bitfield<0> ie;
143 EndBitUnion(StatusReg)
144 
145 BitUnion32(IntCtlReg)
146  Bitfield<31, 29> ipti;
147  Bitfield<28, 26> ippci;
148  // Bits 26-10 are zeros
149  Bitfield<9, 5> vs;
150  // Bits 4-0 are zeros
151 EndBitUnion(IntCtlReg)
152 
153 BitUnion32(SRSCtlReg)
154  // Bits 31-30 are zeros
155  Bitfield<29, 26> hss;
156  // Bits 25-22 are zeros
157  Bitfield<21, 18> eicss;
158  // Bits 17-16 are zeros
159  Bitfield<15, 12> ess;
160  // Bits 11-10 are zeros
161  Bitfield<9, 6> pss;
162  // Bits 5-4 are zeros
163  Bitfield<3, 0> css;
164 EndBitUnion(SRSCtlReg)
165 
166 BitUnion32(SRSMapReg)
167  Bitfield<31, 28> ssv7;
168  Bitfield<27, 24> ssv6;
169  Bitfield<23, 20> ssv5;
170  Bitfield<19, 16> ssv4;
171  Bitfield<15, 12> ssv3;
172  Bitfield<11, 8> ssv2;
173  Bitfield<7, 4> ssv1;
174  Bitfield<3, 0> ssv0;
175 EndBitUnion(SRSMapReg)
176 
177 BitUnion32(CauseReg)
178  Bitfield<31> bd;
179  Bitfield<30> ti;
180  Bitfield<29, 28> ce;
181  Bitfield<27> dc;
182  Bitfield<26> pci;
183  // Bits 25-24 are zeros
184  Bitfield<23> iv;
185  Bitfield<22> wp;
186  // Bits 21-16 are zeros
187  Bitfield<15, 10> ripl;
188  SubBitUnion(ip, 15, 8)
189  Bitfield<15> ip7;
190  Bitfield<14> ip6;
191  Bitfield<13> ip5;
192  Bitfield<12> ip4;
193  Bitfield<11> ip3;
194  Bitfield<10> ip2;
195  Bitfield<9> ip1;
196  Bitfield<8> ip0;
198  // Bit 7 is zero
199  Bitfield<6, 2> excCode;
200  // Bits 1-0 are zeros
201 EndBitUnion(CauseReg)
202 
203 BitUnion32(PRIdReg)
204  Bitfield<31, 24> coOp;
205  Bitfield<23, 16> coId;
206  Bitfield<15, 8> procId;
207  Bitfield<7, 0> rev;
208 EndBitUnion(PRIdReg)
209 
210 BitUnion32(EBaseReg)
211  // Bit 31 is one
212  // Bit 30 is zero
213  Bitfield<29, 12> exceptionBase;
214  // Bits 11-10 are zeros
215  Bitfield<9, 9> cpuNum;
216 EndBitUnion(EBaseReg)
217 
218 BitUnion32(ConfigReg)
219  Bitfield<31> m;
220  Bitfield<30, 28> k23;
221  Bitfield<27, 25> ku;
222  Bitfield<24, 16> impl;
223  Bitfield<15> be;
224  Bitfield<14, 13> at;
225  Bitfield<12, 10> ar;
226  Bitfield<9, 7> mt;
227  // Bits 6-4 are zeros
228  Bitfield<3> vi;
229  Bitfield<2, 0> k0;
230 EndBitUnion(ConfigReg)
231 
232 BitUnion32(Config1Reg)
233  Bitfield<31> m;
234  Bitfield<30, 25> mmuSize;
235  Bitfield<24, 22> is;
236  Bitfield<21, 19> il;
237  Bitfield<18, 16> ia;
238  Bitfield<15, 13> ds;
239  Bitfield<12, 10> dl;
240  Bitfield<9, 7> da;
241  Bitfield<6> c2;
242  Bitfield<5> md;
243  Bitfield<4> pc;
244  Bitfield<3> wr;
245  Bitfield<2> ca;
246  Bitfield<1> ep;
247  Bitfield<0> fp;
248 EndBitUnion(Config1Reg)
249 
250 BitUnion32(Config2Reg)
251  Bitfield<31> m;
252  Bitfield<30, 28> tu;
253  Bitfield<27, 24> ts;
254  Bitfield<23, 20> tl;
255  Bitfield<19, 16> ta;
256  Bitfield<15, 12> su;
257  Bitfield<11, 8> ss;
258  Bitfield<7, 4> sl;
259  Bitfield<3, 0> sa;
260 EndBitUnion(Config2Reg)
261 
262 BitUnion32(Config3Reg)
263  Bitfield<31> m;
264  // Bits 30-11 are zeros
265  Bitfield<10> dspp;
266  // Bits 9-8 are zeros
267  Bitfield<7> lpa;
268  Bitfield<6> veic;
269  Bitfield<5> vint;
270  Bitfield<4> sp;
271  // Bit 3 is zero
272  Bitfield<2> mt;
273  Bitfield<1> sm;
274  Bitfield<0> tl;
275 EndBitUnion(Config3Reg)
276 
277 BitUnion64(WatchLoReg)
278  Bitfield<63, 3> vaddr;
279  Bitfield<2> i;
280  Bitfield<1> r;
281  Bitfield<0> w;
282 EndBitUnion(WatchLoReg)
283 
284 BitUnion32(WatchHiReg)
285  Bitfield<31> m;
286  Bitfield<30> g;
287  // Bits 29-24 are zeros
288  Bitfield<23, 16> asid;
289  // Bits 15-12 are zeros
290  Bitfield<11, 3> mask;
291  Bitfield<2> i;
292  Bitfield<1> r;
293  Bitfield<0> w;
294 EndBitUnion(WatchHiReg)
295 
296 BitUnion32(PerfCntCtlReg)
297  Bitfield<31> m;
298  Bitfield<30> w;
299  // Bits 29-11 are zeros
300  Bitfield<10, 5> event;
301  Bitfield<4> ie;
302  Bitfield<3> u;
303  Bitfield<2> s;
304  Bitfield<1> k;
305  Bitfield<0> exl;
306 EndBitUnion(PerfCntCtlReg)
307 
308 BitUnion32(CacheErrReg)
309  Bitfield<31> er;
310  Bitfield<30> ec;
311  Bitfield<29> ed;
312  Bitfield<28> et;
313  Bitfield<27> es;
314  Bitfield<26> ee;
315  Bitfield<25> eb;
316  Bitfield<24, 22> impl;
317  Bitfield<22, 0> index;
318 EndBitUnion(CacheErrReg)
319 
320 BitUnion32(TagLoReg)
321  Bitfield<31, 8> pTagLo;
322  Bitfield<7, 6> pState;
323  Bitfield<5> l;
324  Bitfield<4, 3> impl;
325  // Bits 2-1 are zeros
326  Bitfield<0> p;
327 EndBitUnion(TagLoReg)
328 
329 } // namespace MipsISA
330 } // namespace gem5
331 
332 #endif
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition: bitunion.hh:494
EndBitUnion(DebugReg) BitUnion32(TraceControlReg) Bitfield< 31 > ts
Bitfield< 9, 5 > vs
Bitfield< 26 > ee
Bitfield< 7, 4 > ssv1
Bitfield< 31 > cu3
Bitfield< 30, 28 > tu
Bitfield< 30, 25 > mmuSize
Bitfield< 14 > ip6
Bitfield< 28 > et
Bitfield< 10 > ip2
Bitfield< 4 > um
Bitfield< 10 > im2
BitUnion32(DebugReg) Bitfield< 31 > dbd
Bitfield< 12, 11 > maskx
Bitfield< 3, 0 > css
Bitfield< 19, 16 > impl
Definition: mt_constants.hh:90
Bitfield< 0 > ie
Bitfield< 5 > md
Bitfield< 25 > re
Bitfield< 4 > pc
Bitfield< 12, 8 > aseDn
Bitfield< 3 > vi
Bitfield< 22 > s
Definition: dt_constants.hh:82
Bitfield< 27, 25 > ku
Bitfield< 21 > ts
Bitfield< 9 > im1
Bitfield< 15, 13 > ds
Bitfield< 26 > pci
Bitfield< 7, 6 > pState
Bitfield< 15, 12 > ssv3
Bitfield< 14, 13 > at
Bitfield< 9 > ip1
Bitfield< 19 > nmi
Bitfield< 7, 4 > sl
Bitfield< 10, 5 > event
Bitfield< 12, 5 > asid
Definition: dt_constants.hh:85
Bitfield< 24, 22 > is
Bitfield< 24 > mx
Bitfield< 19, 16 > ta
Bitfield< 21, 18 > eicss
Bitfield< 27 > es
Bitfield< 20 > sr
Bitfield< 0 > fp
Bitfield< 11, 8 > ssv2
Bitfield< 9, 9 > cpuNum
Bitfield< 23 > px
Bitfield< 3, 0 > ssv0
Bitfield< 23, 20 > tl
Bitfield< 12 > im4
Bitfield< 1 > ep
Bitfield< 7 > lpa
Bitfield< 19, 16 > ssv4
Bitfield< 39, 13 > vpn2
Bitfield< 12, 11 > vpn2x
Bitfield< 4 > sp
Bitfield< 12, 10 > dl
Bitfield< 13 > ip5
Bitfield< 23, 16 > coId
Bitfield< 9, 6 > pss
Bitfield< 10 > dspp
Bitfield< 2, 0 > k0
Bitfield< 15, 10 > ipl
Bitfield< 1 > v
Bitfield< 5, 3 > c
Bitfield< 29 > elpa
Bitfield< 7, 0 > rev
Bitfield< 29 > cu1
Bitfield< 27 > dc
EndSubBitUnion(ejtagVer) Bitfield< 14
Bitfield< 22 > wp
Bitfield< 2 > ca
Bitfield< 29, 28 > ce
Bitfield< 15 > da
Definition: mt_constants.hh:91
Bitfield< 5 > l
Bitfield< 29 > ed
Bitfield< 8 > ip0
Bitfield< 30, 0 > index
Bitfield< 6, 2 > excCode
Bitfield< 13 > im5
Bitfield< 25 > d
Definition: dt_constants.hh:79
Bitfield< 15, 12 > su
Bitfield< 22 > bev
Bitfield< 14 > im6
Bitfield< 6 > sx
Bitfield< 5 > ux
Bitfield< 30, 28 > k23
Bitfield< 2 > erl
Bitfield< 22, 4 > badVPN2
Bitfield< 4 > g
Definition: dt_constants.hh:86
Bitfield< 25 > eb
Bitfield< 15, 10 > ripl
Bitfield< 1 > sm
Bitfield< 21, 19 > il
Bitfield< 21 > u
Definition: dt_constants.hh:83
Bitfield< 29, 6 > pfn
Bitfield< 0 > p
Bitfield< 28 > esp
Bitfield< 3 > r0
Bitfield< 30 > ti
Bitfield< 15, 12 > ess
Bitfield< 27, 24 > ssv6
Bitfield< 26 > fr
Bitfield< 18, 16 > ia
Bitfield< 15, 8 > procId
Bitfield< 5 > vint
Bitfield< 12 > ip4
Bitfield< 23, 20 > ssv5
Bitfield< 15 > be
Bitfield< 11, 8 > ss
Bitfield< 23 > iv
Bitfield< 23 > k
Definition: dt_constants.hh:81
Bitfield< 11 > im3
Bitfield< 28, 26 > ippci
Bitfield< 6 > c2
Bitfield< 3 > wr
Bitfield< 11 > ip3
Bitfield< 8 > im0
Bitfield< 9, 7 > mt
Bitfield< 1 > exl
Bitfield< 2 > i
Bitfield< 12, 10 > ar
Bitfield< 6 > veic
Bitfield< 30 > cu2
Bitfield< 0 > w
Bitfield< 3, 0 > sa
Bitfield< 30 > ec
SubBitUnion(ejtagVer, 17, 15) Bitfield< 17 > ejtagVer2
Bitfield< 28 > cu0
Bitfield< 4, 3 > ksu
Bitfield< 15, 2 > bd
Definition: types.hh:79
bool ip(TxDesc *d)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

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