gem5  v22.0.0.2
pm4_queues.hh
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32 
33 #ifndef __DEV_AMDGPU_PM4_QUEUES_HH__
34 #define __DEV_AMDGPU_PM4_QUEUES_HH__
35 
36 namespace gem5
37 {
38 
44 typedef struct GEM5_PACKED
45 {
46  union
47  {
48  struct
49  {
52  };
53  uint64_t mqdReadIndex;
54  };
63  uint32_t disable_queue;
64  uint32_t reserved_107;
69  uint32_t reserved_112;
70  uint32_t reserved_113;
73  uint32_t cp_packet_id_lo;
74  uint32_t cp_packet_id_hi;
79  uint32_t gds_save_mask_lo;
80  uint32_t gds_save_mask_hi;
85  union
86  {
87  struct
88  {
89  uint32_t mqd_base_addr_lo;
90  uint32_t mqd_base_addr_hi;
91  };
92  uint64_t mqdBase;
93  };
94  uint32_t hqd_active;
95  uint32_t hqd_vmid;
99  uint32_t hqd_quantum;
100  union
101  {
102  struct
103  {
104  uint32_t hqd_pq_base_lo;
105  uint32_t hqd_pq_base_hi;
106  };
107  uint64_t base;
108  };
109  union
110  {
111  uint32_t hqd_pq_rptr;
112  uint32_t rptr;
113  };
114  union
115  {
116  struct
117  {
120  };
121  uint64_t aqlRptr;
122  };
125  union
126  {
128  uint32_t doorbell;
129  };
130  uint32_t reserved_144;
131  uint32_t hqd_pq_control;
132  union
133  {
134  struct
135  {
138  };
140  };
141  union
142  {
143  uint32_t hqd_ib_rptr;
144  uint32_t ibRptr;
145  };
146  uint32_t hqd_ib_control;
147  uint32_t hqd_iq_timer;
148  uint32_t hqd_iq_rptr;
151  uint32_t cp_hqd_sema_cmd;
152  uint32_t cp_hqd_msg_type;
159  uint32_t cp_mqd_control;
165  uint32_t cp_hqd_eop_rptr;
166  uint32_t cp_hqd_eop_wptr;
176  uint32_t cp_hqd_error;
178  union
179  {
181  uint32_t aql;
182  };
185 } QueueDesc;
186 
192 typedef struct GEM5_PACKED
193 {
195  union
196  {
197  struct
198  {
201  };
202  uint64_t rb_base;
203  };
243  uint32_t reserved_42;
244  uint32_t reserved_43;
245  uint32_t reserved_44;
246  uint32_t reserved_45;
247  uint32_t reserved_46;
248  uint32_t reserved_47;
249  uint32_t reserved_48;
250  uint32_t reserved_49;
251  uint32_t reserved_50;
252  uint32_t reserved_51;
253  uint32_t reserved_52;
254  uint32_t reserved_53;
255  uint32_t reserved_54;
256  uint32_t reserved_55;
257  uint32_t reserved_56;
258  uint32_t reserved_57;
259  uint32_t reserved_58;
260  uint32_t reserved_59;
261  uint32_t reserved_60;
262  uint32_t reserved_61;
263  uint32_t reserved_62;
264  uint32_t reserved_63;
265  uint32_t reserved_64;
266  uint32_t reserved_65;
267  uint32_t reserved_66;
268  uint32_t reserved_67;
269  uint32_t reserved_68;
270  uint32_t reserved_69;
271  uint32_t reserved_70;
272  uint32_t reserved_71;
273  uint32_t reserved_72;
274  uint32_t reserved_73;
275  uint32_t reserved_74;
276  uint32_t reserved_75;
277  uint32_t reserved_76;
278  uint32_t reserved_77;
279  uint32_t reserved_78;
280  uint32_t reserved_79;
281  uint32_t reserved_80;
282  uint32_t reserved_81;
283  uint32_t reserved_82;
284  uint32_t reserved_83;
285  uint32_t reserved_84;
286  uint32_t reserved_85;
287  uint32_t reserved_86;
288  uint32_t reserved_87;
289  uint32_t reserved_88;
290  uint32_t reserved_89;
291  uint32_t reserved_90;
292  uint32_t reserved_91;
293  uint32_t reserved_92;
294  uint32_t reserved_93;
295  uint32_t reserved_94;
296  uint32_t reserved_95;
297  uint32_t reserved_96;
298  uint32_t reserved_97;
299  uint32_t reserved_98;
300  uint32_t reserved_99;
301  uint32_t reserved_100;
302  uint32_t reserved_101;
303  uint32_t reserved_102;
304  uint32_t reserved_103;
305  uint32_t reserved_104;
306  uint32_t reserved_105;
307  uint32_t reserved_106;
308  uint32_t reserved_107;
309  uint32_t reserved_108;
310  uint32_t reserved_109;
311  uint32_t reserved_110;
312  uint32_t reserved_111;
313  uint32_t reserved_112;
314  uint32_t reserved_113;
315  uint32_t reserved_114;
316  uint32_t reserved_115;
317  uint32_t reserved_116;
318  uint32_t reserved_117;
319  uint32_t reserved_118;
320  uint32_t reserved_119;
321  uint32_t reserved_120;
322  uint32_t reserved_121;
323  uint32_t reserved_122;
324  uint32_t reserved_123;
325  uint32_t reserved_124;
326  uint32_t reserved_125;
327  /* reserved_126,127: repurposed for driver-internal use */
328  uint32_t sdma_engine_id;
329  uint32_t sdma_queue_id;
330 } SDMAQueueDesc;
331 
332 /* The Primary Queue has extra attributes, which will be stored separately. */
333 typedef struct PrimaryQueue : QueueDesc
334 {
335  union
336  {
337  struct
338  {
339  uint32_t queueRptrAddrLo;
340  uint32_t queueRptrAddrHi;
341  };
343  };
344  union
345  {
346  struct
347  {
348  uint32_t queueWptrLo;
349  uint32_t queueWptrHi;
350  };
352  };
353  uint32_t doorbellOffset;
354  uint32_t doorbellRangeLo;
355  uint32_t doorbellRangeHi;
356 } PrimaryQueue;
357 
361 class PM4Queue
362 {
363  int _id;
364 
365  /* Queue descriptor read from the system memory of the simulated system. */
367 
377  bool _ib;
379  public:
380  PM4Queue() : _id(0), q(nullptr), _wptr(0), _offset(0), _processing(false),
381  _ib(false), _pkt(nullptr) {}
384  _processing(false), _ib(false), _pkt(nullptr) {}
387  _processing(false), _ib(false), _pkt(pkt) {}
388 
389  QueueDesc *getMQD() { return q; }
390  int id() { return _id; }
391  Addr mqdBase() { return q->mqdBase; }
392  Addr base() { return q->base; }
393  Addr ibBase() { return q->ibBase; }
394 
395  Addr
397  {
398  if (ib()) return q->ibBase + q->ibRptr;
399  else return q->base + q->rptr;
400  }
401 
402  Addr
404  {
405  if (ib()) return q->ibBase + _ibWptr;
406  else return q->base + _wptr;
407  }
408 
409  Addr
411  {
412  if (ib()) return q->ibRptr;
413  else return q->rptr;
414  }
415 
416  Addr
418  {
419  if (ib()) return _ibWptr;
420  else return _wptr;
421  }
422 
423  Addr offset() { return _offset; }
424  bool processing() { return _processing; }
425  bool ib() { return _ib; }
426 
427  void id(int value) { _id = value; }
428  void base(Addr value) { q->base = value; }
429  void ibBase(Addr value) { q->ibBase = value; }
430 
438  void
440  {
441  if (ib()) q->ibRptr = _ibWptr;
442  else q->rptr = _wptr;
443  }
444 
445  void
446  incRptr(Addr value)
447  {
448  if (ib()) q->ibRptr += value;
449  else q->rptr += value;
450  }
451 
452  void
453  rptr(Addr value)
454  {
455  if (ib()) q->ibRptr = value;
456  else q->rptr = value;
457  }
458 
459  void
460  wptr(Addr value)
461  {
462  if (ib()) _ibWptr = value;
463  else _wptr = value;
464  }
465 
466  void offset(Addr value) { _offset = value; }
467  void processing(bool value) { _processing = value; }
468  void ib(bool value) { _ib = value; }
469  uint32_t me() { if (_pkt) return _pkt->me; else return 0; }
470  uint32_t pipe() { if (_pkt) return _pkt->pipe; else return 0; }
471  uint32_t queue() { if (_pkt) return _pkt->queueSlot; else return 0; }
472  bool privileged() { assert(_pkt); return _pkt->queueSel == 0 ? 1 : 0; }
473 };
474 
475 } // namespace gem5
476 
477 #endif // __DEV_AMDGPU_PM4_QUEUES_HH__
gem5::GEM5_PACKED::hqd_pq_rptr
uint32_t hqd_pq_rptr
Definition: pm4_queues.hh:111
gem5::PM4Queue::ibBase
Addr ibBase()
Definition: pm4_queues.hh:393
gem5::GEM5_PACKED::reserved_113
uint32_t reserved_113
Definition: pm4_queues.hh:70
gem5::GEM5_PACKED::cp_hqd_eop_wptr
uint32_t cp_hqd_eop_wptr
Definition: pm4_queues.hh:166
gem5::GEM5_PACKED::reserved_118
uint32_t reserved_118
Definition: pm4_queues.hh:319
gem5::GEM5_PACKED::reserved_90
uint32_t reserved_90
Definition: pm4_queues.hh:291
gem5::GEM5_PACKED::gds_save_base_addr_hi
uint32_t gds_save_base_addr_hi
Definition: pm4_queues.hh:78
gem5::GEM5_PACKED::reserved_72
uint32_t reserved_72
Definition: pm4_queues.hh:273
gem5::PM4Queue::ibBase
void ibBase(Addr value)
Definition: pm4_queues.hh:429
gem5::GEM5_PACKED::cp_hqd_cntl_stack_offset
uint32_t cp_hqd_cntl_stack_offset
Definition: pm4_queues.hh:171
gem5::GEM5_PACKED::reserved_124
uint32_t reserved_124
Definition: pm4_queues.hh:325
gem5::GEM5_PACKED::reserved_121
uint32_t reserved_121
Definition: pm4_queues.hh:322
gem5::GEM5_PACKED
PM4 packets.
Definition: pm4_defines.hh:77
gem5::GEM5_PACKED::hqd_iq_timer
uint32_t hqd_iq_timer
Definition: pm4_queues.hh:147
gem5::PM4Queue::queue
uint32_t queue()
Definition: pm4_queues.hh:471
gem5::GEM5_PACKED::reserved_112
uint32_t reserved_112
Definition: pm4_queues.hh:69
gem5::GEM5_PACKED::rptr
uint32_t rptr
Definition: pm4_queues.hh:112
gem5::PM4Queue::processing
bool processing()
Definition: pm4_queues.hh:424
gem5::GEM5_PACKED::sdmax_rlcx_doorbell
uint32_t sdmax_rlcx_doorbell
Definition: pm4_queues.hh:219
gem5::GEM5_PACKED::reserved_94
uint32_t reserved_94
Definition: pm4_queues.hh:295
gem5::GEM5_PACKED::hqd_pq_doorbell_control
uint32_t hqd_pq_doorbell_control
Definition: pm4_queues.hh:127
gem5::GEM5_PACKED::reserved_65
uint32_t reserved_65
Definition: pm4_queues.hh:266
gem5::GEM5_PACKED::cp_packet_id_hi
uint32_t cp_packet_id_hi
Definition: pm4_queues.hh:74
gem5::QueueDesc
struct gem5::GEM5_PACKED QueueDesc
Queue descriptor with relevant MQD attributes.
gem5::PM4Queue::base
void base(Addr value)
Definition: pm4_queues.hh:428
gem5::GEM5_PACKED::mqd_base_addr_hi
uint32_t mqd_base_addr_hi
Definition: pm4_queues.hh:90
gem5::GEM5_PACKED::hqd_queue_priority
uint32_t hqd_queue_priority
Definition: pm4_queues.hh:98
gem5::GEM5_PACKED::cp_hqd_eop_base_addr_hi
uint32_t cp_hqd_eop_base_addr_hi
Definition: pm4_queues.hh:163
gem5::GEM5_PACKED::cp_hqd_wg_state_offset
uint32_t cp_hqd_wg_state_offset
Definition: pm4_queues.hh:173
gem5::GEM5_PACKED::cp_mqd_readindex_lo
uint32_t cp_mqd_readindex_lo
Definition: pm4_queues.hh:50
gem5::GEM5_PACKED::sdmax_rlcx_preempt
uint32_t sdmax_rlcx_preempt
Definition: pm4_queues.hh:227
gem5::GEM5_PACKED::cp_packet_exe_status_hi
uint32_t cp_packet_exe_status_hi
Definition: pm4_queues.hh:76
gem5::GEM5_PACKED::reserved_63
uint32_t reserved_63
Definition: pm4_queues.hh:264
gem5::GEM5_PACKED::reserved_82
uint32_t reserved_82
Definition: pm4_queues.hh:283
gem5::GEM5_PACKED::cp_hqd_pq_wptr_lo
uint32_t cp_hqd_pq_wptr_lo
Definition: pm4_queues.hh:183
gem5::GEM5_PACKED::sdmax_rlcx_rb_cntl
uint32_t sdmax_rlcx_rb_cntl
Definition: pm4_queues.hh:194
gem5::GEM5_PACKED::reserved_50
uint32_t reserved_50
Definition: pm4_queues.hh:251
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data0
uint32_t sdmax_rlcx_midcmd_data0
Definition: pm4_queues.hh:233
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_cntl
uint32_t sdmax_rlcx_midcmd_cntl
Definition: pm4_queues.hh:242
gem5::PM4Queue
Class defining a PM4 queue.
Definition: pm4_queues.hh:361
gem5::PM4Queue::id
void id(int value)
Definition: pm4_queues.hh:427
gem5::PrimaryQueue::queueWptrLo
uint32_t queueWptrLo
Definition: pm4_queues.hh:348
gem5::GEM5_PACKED::reserved_73
uint32_t reserved_73
Definition: pm4_queues.hh:274
gem5::GEM5_PACKED::cp_mqd_save_end_time_hi
uint32_t cp_mqd_save_end_time_hi
Definition: pm4_queues.hh:58
gem5::GEM5_PACKED::sdmax_rlcx_doorbell_log
uint32_t sdmax_rlcx_doorbell_log
Definition: pm4_queues.hh:221
gem5::PM4Queue::_ib
bool _ib
Definition: pm4_queues.hh:377
gem5::PM4Queue::pipe
uint32_t pipe()
Definition: pm4_queues.hh:470
gem5::PM4Queue::fastforwardRptr
void fastforwardRptr()
It seems that PM4 nop packets with count 0x3fff, not only do not consider the count value,...
Definition: pm4_queues.hh:439
gem5::GEM5_PACKED::cp_hqd_atomic0_preop_lo
uint32_t cp_hqd_atomic0_preop_lo
Definition: pm4_queues.hh:153
gem5::PM4Queue::mqdBase
Addr mqdBase()
Definition: pm4_queues.hh:391
gem5::GEM5_PACKED::hqd_vmid
uint32_t hqd_vmid
Definition: pm4_queues.hh:95
gem5::PM4Queue::rptr
void rptr(Addr value)
Definition: pm4_queues.hh:453
gem5::GEM5_PACKED::reserved_105
uint32_t reserved_105
Definition: pm4_queues.hh:306
gem5::GEM5_PACKED::reserved_66
uint32_t reserved_66
Definition: pm4_queues.hh:267
gem5::GEM5_PACKED::ctx_save_base_addr_lo
uint32_t ctx_save_base_addr_lo
Definition: pm4_queues.hh:81
gem5::GEM5_PACKED::reserved_61
uint32_t reserved_61
Definition: pm4_queues.hh:262
gem5::PM4Queue::wptr
void wptr(Addr value)
Definition: pm4_queues.hh:460
gem5::GEM5_PACKED::reserved_52
uint32_t reserved_52
Definition: pm4_queues.hh:253
gem5::GEM5_PACKED::queueSel
uint32_t queueSel
Definition: pm4_defines.hh:123
gem5::GEM5_PACKED::reserved_43
uint32_t reserved_43
Definition: pm4_queues.hh:244
gem5::GEM5_PACKED::cp_hqd_cntl_stack_size
uint32_t cp_hqd_cntl_stack_size
Definition: pm4_queues.hh:172
gem5::GEM5_PACKED::reserved_109
uint32_t reserved_109
Definition: pm4_queues.hh:310
gem5::GEM5_PACKED::hqd_pq_wptr_poll_addr_hi
uint32_t hqd_pq_wptr_poll_addr_hi
Definition: pm4_queues.hh:124
gem5::GEM5_PACKED::gds_save_mask_lo
uint32_t gds_save_mask_lo
Definition: pm4_queues.hh:79
gem5::GEM5_PACKED::reserved_95
uint32_t reserved_95
Definition: pm4_queues.hh:296
gem5::GEM5_PACKED::reserved_44
uint32_t reserved_44
Definition: pm4_queues.hh:245
gem5::GEM5_PACKED::sdmax_rlcx_rb_rptr_addr_lo
uint32_t sdmax_rlcx_rb_rptr_addr_lo
Definition: pm4_queues.hh:210
gem5::GEM5_PACKED::reserved_46
uint32_t reserved_46
Definition: pm4_queues.hh:247
gem5::GEM5_PACKED::cp_mqd_restore_end_time_lo
uint32_t cp_mqd_restore_end_time_lo
Definition: pm4_queues.hh:61
gem5::GEM5_PACKED::cp_pq_exe_status_lo
uint32_t cp_pq_exe_status_lo
Definition: pm4_queues.hh:71
gem5::GEM5_PACKED::sdmax_rlcx_ib_size
uint32_t sdmax_rlcx_ib_size
Definition: pm4_queues.hh:216
gem5::GEM5_PACKED::hqd_pq_base_lo
uint32_t hqd_pq_base_lo
Definition: pm4_queues.hh:104
gem5::PM4Queue::me
uint32_t me()
Definition: pm4_queues.hh:469
gem5::GEM5_PACKED::hqd_ib_base_addr_lo
uint32_t hqd_ib_base_addr_lo
Definition: pm4_queues.hh:136
gem5::GEM5_PACKED::reserved_86
uint32_t reserved_86
Definition: pm4_queues.hh:287
gem5::GEM5_PACKED::ibBase
Addr ibBase
Definition: pm4_queues.hh:139
gem5::PrimaryQueue::queueRptrAddrHi
uint32_t queueRptrAddrHi
Definition: pm4_queues.hh:340
gem5::GEM5_PACKED::sdmax_rlcx_rb_wptr_poll_cntl
uint32_t sdmax_rlcx_rb_wptr_poll_cntl
Definition: pm4_queues.hh:208
gem5::GEM5_PACKED::reserved_115
uint32_t reserved_115
Definition: pm4_queues.hh:316
gem5::PrimaryQueue
gem5::PrimaryQueue PrimaryQueue
gem5::GEM5_PACKED::reserved_120
uint32_t reserved_120
Definition: pm4_queues.hh:321
gem5::PrimaryQueue::queueWptr
Addr queueWptr
Definition: pm4_queues.hh:351
gem5::GEM5_PACKED::reserved_67
uint32_t reserved_67
Definition: pm4_queues.hh:268
gem5::GEM5_PACKED::sdmax_rlcx_skip_cntl
uint32_t sdmax_rlcx_skip_cntl
Definition: pm4_queues.hh:217
gem5::GEM5_PACKED::hqd_pq_rptr_report_addr_lo
uint32_t hqd_pq_rptr_report_addr_lo
Definition: pm4_queues.hh:118
gem5::PrimaryQueue
Definition: pm4_queues.hh:333
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data6
uint32_t sdmax_rlcx_midcmd_data6
Definition: pm4_queues.hh:239
gem5::GEM5_PACKED::cp_mqd_restore_start_time_hi
uint32_t cp_mqd_restore_start_time_hi
Definition: pm4_queues.hh:60
gem5::GEM5_PACKED::reserved_96
uint32_t reserved_96
Definition: pm4_queues.hh:297
gem5::GEM5_PACKED::reserved_122
uint32_t reserved_122
Definition: pm4_queues.hh:323
gem5::GEM5_PACKED::cp_hqd_atomic1_preop_hi
uint32_t cp_hqd_atomic1_preop_hi
Definition: pm4_queues.hh:156
gem5::GEM5_PACKED::hqd_pq_rptr_report_addr_hi
uint32_t hqd_pq_rptr_report_addr_hi
Definition: pm4_queues.hh:119
gem5::GEM5_PACKED::cp_hqd_dma_offload
uint32_t cp_hqd_dma_offload
Definition: pm4_queues.hh:150
gem5::GEM5_PACKED::sdmax_rlcx_ib_sub_remain
uint32_t sdmax_rlcx_ib_sub_remain
Definition: pm4_queues.hh:226
gem5::GEM5_PACKED::disable_queue
uint32_t disable_queue
Definition: pm4_queues.hh:63
gem5::GEM5_PACKED::reserved_77
uint32_t reserved_77
Definition: pm4_queues.hh:278
gem5::GEM5_PACKED::mqdReadIndex
uint64_t mqdReadIndex
Definition: pm4_queues.hh:53
gem5::GEM5_PACKED::reserved_123
uint32_t reserved_123
Definition: pm4_queues.hh:324
gem5::GEM5_PACKED::reserved_102
uint32_t reserved_102
Definition: pm4_queues.hh:303
gem5::GEM5_PACKED::sdmax_rlcx_rb_rptr_hi
uint32_t sdmax_rlcx_rb_rptr_hi
Definition: pm4_queues.hh:205
gem5::GEM5_PACKED::cp_mqd_restore_start_time_lo
uint32_t cp_mqd_restore_start_time_lo
Definition: pm4_queues.hh:59
gem5::PrimaryQueue::queueRptrAddr
Addr queueRptrAddr
Definition: pm4_queues.hh:342
gem5::GEM5_PACKED::hqd_ib_base_addr_hi
uint32_t hqd_ib_base_addr_hi
Definition: pm4_queues.hh:137
gem5::GEM5_PACKED::reserved_47
uint32_t reserved_47
Definition: pm4_queues.hh:248
gem5::PM4Queue::privileged
bool privileged()
Definition: pm4_queues.hh:472
gem5::GEM5_PACKED::cp_hqd_eop_done_events
uint32_t cp_hqd_eop_done_events
Definition: pm4_queues.hh:167
gem5::GEM5_PACKED::cp_hqd_hq_control1
uint32_t cp_hqd_hq_control1
Definition: pm4_queues.hh:161
gem5::GEM5_PACKED::cp_hqd_aql_control
uint32_t cp_hqd_aql_control
Definition: pm4_queues.hh:180
gem5::GEM5_PACKED::reserved_55
uint32_t reserved_55
Definition: pm4_queues.hh:256
gem5::PM4Queue::rptr
Addr rptr()
Definition: pm4_queues.hh:396
gem5::PM4Queue::PM4Queue
PM4Queue(int id, QueueDesc *queue, Addr offset, PM4MapQueues *pkt)
Definition: pm4_queues.hh:385
gem5::GEM5_PACKED::reserved_87
uint32_t reserved_87
Definition: pm4_queues.hh:288
gem5::GEM5_PACKED::gds_cs_ctxsw_cnt2
uint32_t gds_cs_ctxsw_cnt2
Definition: pm4_queues.hh:67
gem5::GEM5_PACKED::hqd_pipe_priority
uint32_t hqd_pipe_priority
Definition: pm4_queues.hh:97
gem5::GEM5_PACKED::reserved_110
uint32_t reserved_110
Definition: pm4_queues.hh:311
gem5::GEM5_PACKED::cp_hqd_atomic0_preop_hi
uint32_t cp_hqd_atomic0_preop_hi
Definition: pm4_queues.hh:154
gem5::GEM5_PACKED::aql
uint32_t aql
Definition: pm4_queues.hh:181
gem5::GEM5_PACKED::cp_hqd_ctx_save_base_addr_lo
uint32_t cp_hqd_ctx_save_base_addr_lo
Definition: pm4_queues.hh:168
gem5::GEM5_PACKED::cp_hqd_msg_type
uint32_t cp_hqd_msg_type
Definition: pm4_queues.hh:152
gem5::GEM5_PACKED::cp_hqd_sema_cmd
uint32_t cp_hqd_sema_cmd
Definition: pm4_queues.hh:151
gem5::GEM5_PACKED::pipe
uint32_t pipe
Definition: pm4_defines.hh:128
gem5::PM4Queue::_ibWptr
Addr _ibWptr
Definition: pm4_queues.hh:374
gem5::GEM5_PACKED::cp_hqd_hq_control0
uint32_t cp_hqd_hq_control0
Definition: pm4_queues.hh:158
gem5::GEM5_PACKED::gds_cs_ctxsw_cnt3
uint32_t gds_cs_ctxsw_cnt3
Definition: pm4_queues.hh:68
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data5
uint32_t sdmax_rlcx_midcmd_data5
Definition: pm4_queues.hh:238
gem5::GEM5_PACKED::reserved_62
uint32_t reserved_62
Definition: pm4_queues.hh:263
gem5::GEM5_PACKED::reserved_51
uint32_t reserved_51
Definition: pm4_queues.hh:252
gem5::GEM5_PACKED::reserved_59
uint32_t reserved_59
Definition: pm4_queues.hh:260
gem5::GEM5_PACKED::hqd_pq_base_hi
uint32_t hqd_pq_base_hi
Definition: pm4_queues.hh:105
gem5::GEM5_PACKED::cp_hqd_ctx_save_base_addr_hi
uint32_t cp_hqd_ctx_save_base_addr_hi
Definition: pm4_queues.hh:169
gem5::GEM5_PACKED::rb_base
uint64_t rb_base
Definition: pm4_queues.hh:202
gem5::GEM5_PACKED::ctx_save_base_addr_hi
uint32_t ctx_save_base_addr_hi
Definition: pm4_queues.hh:82
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data7
uint32_t sdmax_rlcx_midcmd_data7
Definition: pm4_queues.hh:240
gem5::GEM5_PACKED::cp_hqd_hq_status1
uint32_t cp_hqd_hq_status1
Definition: pm4_queues.hh:160
gem5::GEM5_PACKED::me
uint32_t me
Definition: pm4_defines.hh:127
gem5::GEM5_PACKED::sdmax_rlcx_ib_base_hi
uint32_t sdmax_rlcx_ib_base_hi
Definition: pm4_queues.hh:215
gem5::GEM5_PACKED::cp_mqd_save_start_time_hi
uint32_t cp_mqd_save_start_time_hi
Definition: pm4_queues.hh:56
gem5::GEM5_PACKED::reserved_103
uint32_t reserved_103
Definition: pm4_queues.hh:304
gem5::GEM5_PACKED::sdmax_rlcx_status
uint32_t sdmax_rlcx_status
Definition: pm4_queues.hh:220
gem5::GEM5_PACKED::reserved_53
uint32_t reserved_53
Definition: pm4_queues.hh:254
gem5::GEM5_PACKED::reserved_78
uint32_t reserved_78
Definition: pm4_queues.hh:279
gem5::GEM5_PACKED::cp_mqd_save_end_time_lo
uint32_t cp_mqd_save_end_time_lo
Definition: pm4_queues.hh:57
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data4
uint32_t sdmax_rlcx_midcmd_data4
Definition: pm4_queues.hh:237
gem5::GEM5_PACKED::reserved_58
uint32_t reserved_58
Definition: pm4_queues.hh:259
gem5::GEM5_PACKED::ibRptr
uint32_t ibRptr
Definition: pm4_queues.hh:144
gem5::GEM5_PACKED::hqd_quantum
uint32_t hqd_quantum
Definition: pm4_queues.hh:99
gem5::GEM5_PACKED::reserved_56
uint32_t reserved_56
Definition: pm4_queues.hh:257
gem5::GEM5_PACKED::reserved_116
uint32_t reserved_116
Definition: pm4_queues.hh:317
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PrimaryQueue::queueRptrAddrLo
uint32_t queueRptrAddrLo
Definition: pm4_queues.hh:339
gem5::PM4Queue::getRptr
Addr getRptr()
Definition: pm4_queues.hh:410
gem5::GEM5_PACKED::cp_packet_exe_status_lo
uint32_t cp_packet_exe_status_lo
Definition: pm4_queues.hh:75
gem5::GEM5_PACKED::reserved_42
uint32_t reserved_42
Definition: pm4_queues.hh:243
gem5::PM4Queue::getMQD
QueueDesc * getMQD()
Definition: pm4_queues.hh:389
gem5::PM4Queue::_offset
Addr _offset
Definition: pm4_queues.hh:375
gem5::GEM5_PACKED::reserved_119
uint32_t reserved_119
Definition: pm4_queues.hh:320
gem5::PrimaryQueue::doorbellOffset
uint32_t doorbellOffset
Definition: pm4_queues.hh:353
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data1
uint32_t sdmax_rlcx_midcmd_data1
Definition: pm4_queues.hh:234
gem5::GEM5_PACKED::queueSlot
uint32_t queueSlot
Definition: pm4_defines.hh:129
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data8
uint32_t sdmax_rlcx_midcmd_data8
Definition: pm4_queues.hh:241
gem5::GEM5_PACKED::sdmax_rlcx_rb_rptr
uint32_t sdmax_rlcx_rb_rptr
Definition: pm4_queues.hh:204
gem5::GEM5_PACKED::reserved_81
uint32_t reserved_81
Definition: pm4_queues.hh:282
gem5::PM4Queue::processing
void processing(bool value)
Definition: pm4_queues.hh:467
gem5::PM4Queue::q
QueueDesc * q
Definition: pm4_queues.hh:366
gem5::GEM5_PACKED::doorbell
uint32_t doorbell
Definition: pm4_queues.hh:128
gem5::GEM5_PACKED::dynamic_cu_mask_addr_hi
uint32_t dynamic_cu_mask_addr_hi
Definition: pm4_queues.hh:84
gem5::GEM5_PACKED::cp_hqd_eop_base_addr_lo
uint32_t cp_hqd_eop_base_addr_lo
Definition: pm4_queues.hh:162
gem5::GEM5_PACKED::cp_hqd_pq_wptr_hi
uint32_t cp_hqd_pq_wptr_hi
Definition: pm4_queues.hh:184
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data2
uint32_t sdmax_rlcx_midcmd_data2
Definition: pm4_queues.hh:235
gem5::GEM5_PACKED::hqd_ib_control
uint32_t hqd_ib_control
Definition: pm4_queues.hh:146
gem5::GEM5_PACKED::sdmax_rlcx_rb_wptr_poll_addr_hi
uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi
Definition: pm4_queues.hh:229
gem5::GEM5_PACKED::ibBase
uint64_t ibBase
Definition: pm4_defines.hh:323
gem5::GEM5_PACKED::reserved_88
uint32_t reserved_88
Definition: pm4_queues.hh:289
gem5::GEM5_PACKED::reserved_117
uint32_t reserved_117
Definition: pm4_queues.hh:318
gem5::GEM5_PACKED::sdmax_rlcx_ib_rptr
uint32_t sdmax_rlcx_ib_rptr
Definition: pm4_queues.hh:212
gem5::GEM5_PACKED::mqdBase
uint64_t mqdBase
Definition: pm4_queues.hh:92
gem5::PM4Queue::_wptr
Addr _wptr
Most important fields of a PM4 queue are stored in the queue descriptor (i.e., QueueDesc).
Definition: pm4_queues.hh:373
gem5::PM4Queue::offset
void offset(Addr value)
Definition: pm4_queues.hh:466
gem5::GEM5_PACKED::reserved_71
uint32_t reserved_71
Definition: pm4_queues.hh:272
gem5::GEM5_PACKED::reserved_48
uint32_t reserved_48
Definition: pm4_queues.hh:249
gem5::GEM5_PACKED::cp_mqd_save_start_time_lo
uint32_t cp_mqd_save_start_time_lo
Definition: pm4_queues.hh:55
gem5::GEM5_PACKED::sdmax_rlcx_dummy_reg
uint32_t sdmax_rlcx_dummy_reg
Definition: pm4_queues.hh:228
gem5::PM4Queue::getWptr
Addr getWptr()
Definition: pm4_queues.hh:417
gem5::GEM5_PACKED::reserved_108
uint32_t reserved_108
Definition: pm4_queues.hh:309
gem5::GEM5_PACKED::cp_hqd_error
uint32_t cp_hqd_error
Definition: pm4_queues.hh:176
gem5::PM4Queue::_id
int _id
Definition: pm4_queues.hh:363
gem5::GEM5_PACKED::sdmax_rlcx_midcmd_data3
uint32_t sdmax_rlcx_midcmd_data3
Definition: pm4_queues.hh:236
gem5::GEM5_PACKED::hqd_active
uint32_t hqd_active
Definition: pm4_queues.hh:94
gem5::GEM5_PACKED::reserved_98
uint32_t reserved_98
Definition: pm4_queues.hh:299
gem5::GEM5_PACKED::reserved_74
uint32_t reserved_74
Definition: pm4_queues.hh:275
gem5::GEM5_PACKED::sdmax_rlcx_rb_base_hi
uint32_t sdmax_rlcx_rb_base_hi
Definition: pm4_queues.hh:200
gem5::PM4Queue::incRptr
void incRptr(Addr value)
Definition: pm4_queues.hh:446
gem5::GEM5_PACKED::sdmax_rlcx_watermark
uint32_t sdmax_rlcx_watermark
Definition: pm4_queues.hh:222
gem5::GEM5_PACKED::aqlRptr
uint64_t aqlRptr
Definition: pm4_queues.hh:121
gem5::GEM5_PACKED::reserved_99
uint32_t reserved_99
Definition: pm4_queues.hh:300
gem5::GEM5_PACKED::reserved_91
uint32_t reserved_91
Definition: pm4_queues.hh:292
gem5::PM4Queue::_pkt
PM4MapQueues * _pkt
Definition: pm4_queues.hh:378
gem5::GEM5_PACKED::sdma_queue_id
uint32_t sdma_queue_id
Definition: pm4_queues.hh:329
gem5::GEM5_PACKED::reserved_144
uint32_t reserved_144
Definition: pm4_queues.hh:130
gem5::GEM5_PACKED::cp_mqd_control
uint32_t cp_mqd_control
Definition: pm4_queues.hh:159
gem5::PrimaryQueue::queueWptrHi
uint32_t queueWptrHi
Definition: pm4_queues.hh:349
gem5::GEM5_PACKED::sdmax_rlcx_rb_rptr_addr_hi
uint32_t sdmax_rlcx_rb_rptr_addr_hi
Definition: pm4_queues.hh:209
gem5::GEM5_PACKED::cp_hqd_eop_rptr
uint32_t cp_hqd_eop_rptr
Definition: pm4_queues.hh:165
gem5::GEM5_PACKED::sdmax_rlcx_csa_addr_hi
uint32_t sdmax_rlcx_csa_addr_hi
Definition: pm4_queues.hh:225
gem5::GEM5_PACKED::reserved_104
uint32_t reserved_104
Definition: pm4_queues.hh:305
gem5::GEM5_PACKED::mqd_base_addr_lo
uint32_t mqd_base_addr_lo
Definition: pm4_queues.hh:89
gem5::GEM5_PACKED::hqd_iq_rptr
uint32_t hqd_iq_rptr
Definition: pm4_queues.hh:148
gem5::GEM5_PACKED::reserved_45
uint32_t reserved_45
Definition: pm4_queues.hh:246
gem5::PM4Queue::base
Addr base()
Definition: pm4_queues.hh:392
gem5::GEM5_PACKED::hqd_pq_wptr_poll_addr_lo
uint32_t hqd_pq_wptr_poll_addr_lo
Definition: pm4_queues.hh:123
gem5::GEM5_PACKED::sdmax_rlcx_doorbell_offset
uint32_t sdmax_rlcx_doorbell_offset
Definition: pm4_queues.hh:223
gem5::GEM5_PACKED::reserved_97
uint32_t reserved_97
Definition: pm4_queues.hh:298
gem5::GEM5_PACKED::hqd_ib_rptr
uint32_t hqd_ib_rptr
Definition: pm4_queues.hh:143
gem5::GEM5_PACKED::dynamic_cu_mask_addr_lo
uint32_t dynamic_cu_mask_addr_lo
Definition: pm4_queues.hh:83
gem5::GEM5_PACKED::sdmax_rlcx_rb_base
uint32_t sdmax_rlcx_rb_base
Definition: pm4_queues.hh:199
gem5::GEM5_PACKED::sdmax_rlcx_rb_wptr
uint32_t sdmax_rlcx_rb_wptr
Definition: pm4_queues.hh:206
gem5::GEM5_PACKED::reserved_49
uint32_t reserved_49
Definition: pm4_queues.hh:250
gem5::PM4Queue::_processing
bool _processing
Definition: pm4_queues.hh:376
gem5::GEM5_PACKED::reserved_106
uint32_t reserved_106
Definition: pm4_queues.hh:307
gem5::GEM5_PACKED::sdmax_rlcx_csa_addr_lo
uint32_t sdmax_rlcx_csa_addr_lo
Definition: pm4_queues.hh:224
gem5::GEM5_PACKED::cp_mqd_readindex_hi
uint32_t cp_mqd_readindex_hi
Definition: pm4_queues.hh:51
gem5::GEM5_PACKED::reserved_76
uint32_t reserved_76
Definition: pm4_queues.hh:277
gem5::GEM5_PACKED::gds_save_mask_hi
uint32_t gds_save_mask_hi
Definition: pm4_queues.hh:80
gem5::PM4Queue::PM4Queue
PM4Queue()
Definition: pm4_queues.hh:380
gem5::GEM5_PACKED::gds_cs_ctxsw_cnt1
uint32_t gds_cs_ctxsw_cnt1
Definition: pm4_queues.hh:66
gem5::PM4Queue::ib
void ib(bool value)
Definition: pm4_queues.hh:468
gem5::GEM5_PACKED::cp_hqd_eop_wptr_mem
uint32_t cp_hqd_eop_wptr_mem
Definition: pm4_queues.hh:177
gem5::GEM5_PACKED::reserved_125
uint32_t reserved_125
Definition: pm4_queues.hh:326
gem5::GEM5_PACKED::sdma_engine_id
uint32_t sdma_engine_id
Definition: pm4_queues.hh:328
gem5::PM4Queue::offset
Addr offset()
Definition: pm4_queues.hh:423
gem5::GEM5_PACKED::sdmax_rlcx_context_status
uint32_t sdmax_rlcx_context_status
Definition: pm4_queues.hh:218
gem5::GEM5_PACKED::base
uint64_t base
Definition: pm4_queues.hh:107
gem5::GEM5_PACKED::hqd_persistent_state
uint32_t hqd_persistent_state
Definition: pm4_queues.hh:96
gem5::GEM5_PACKED::cp_hqd_hq_status0
uint32_t cp_hqd_hq_status0
Definition: pm4_queues.hh:157
gem5::GEM5_PACKED::sdmax_rlcx_rb_wptr_poll_addr_lo
uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo
Definition: pm4_queues.hh:230
gem5::PrimaryQueue::doorbellRangeHi
uint32_t doorbellRangeHi
Definition: pm4_queues.hh:355
gem5::PM4Queue::id
int id()
Definition: pm4_queues.hh:390
gem5::GEM5_PACKED::reserved_100
uint32_t reserved_100
Definition: pm4_queues.hh:301
gem5::GEM5_PACKED::reserved_68
uint32_t reserved_68
Definition: pm4_queues.hh:269
gem5::GEM5_PACKED::cp_hqd_dequeue_request
uint32_t cp_hqd_dequeue_request
Definition: pm4_queues.hh:149
gem5::GEM5_PACKED::cp_packet_id_lo
uint32_t cp_packet_id_lo
Definition: pm4_queues.hh:73
gem5::GEM5_PACKED::sdmax_rlcx_rb_wptr_hi
uint32_t sdmax_rlcx_rb_wptr_hi
Definition: pm4_queues.hh:207
gem5::GEM5_PACKED::sdmax_rlcx_minor_ptr_update
uint32_t sdmax_rlcx_minor_ptr_update
Definition: pm4_queues.hh:232
gem5::GEM5_PACKED::reserved_69
uint32_t reserved_69
Definition: pm4_queues.hh:270
gem5::GEM5_PACKED::cp_hqd_atomic1_preop_lo
uint32_t cp_hqd_atomic1_preop_lo
Definition: pm4_queues.hh:155
gem5::GEM5_PACKED::cp_pq_exe_status_hi
uint32_t cp_pq_exe_status_hi
Definition: pm4_queues.hh:72
gem5::GEM5_PACKED::cp_hqd_eop_control
uint32_t cp_hqd_eop_control
Definition: pm4_queues.hh:164
gem5::GEM5_PACKED::sdmax_rlcx_ib_base_lo
uint32_t sdmax_rlcx_ib_base_lo
Definition: pm4_queues.hh:214
gem5::PM4Queue::wptr
Addr wptr()
Definition: pm4_queues.hh:403
gem5::GEM5_PACKED::reserved_85
uint32_t reserved_85
Definition: pm4_queues.hh:286
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PrimaryQueue::doorbellRangeLo
uint32_t doorbellRangeLo
Definition: pm4_queues.hh:354
gem5::GEM5_PACKED::reserved_107
uint32_t reserved_107
Definition: pm4_queues.hh:64
gem5::GEM5_PACKED::reserved_114
uint32_t reserved_114
Definition: pm4_queues.hh:315
gem5::GEM5_PACKED::reserved_101
uint32_t reserved_101
Definition: pm4_queues.hh:302
gem5::GEM5_PACKED::reserved_70
uint32_t reserved_70
Definition: pm4_queues.hh:271
gem5::GEM5_PACKED::reserved_89
uint32_t reserved_89
Definition: pm4_queues.hh:290
gem5::GEM5_PACKED::gds_save_base_addr_lo
uint32_t gds_save_base_addr_lo
Definition: pm4_queues.hh:77
gem5::GEM5_PACKED::reserved_79
uint32_t reserved_79
Definition: pm4_queues.hh:280
gem5::GEM5_PACKED::reserved_57
uint32_t reserved_57
Definition: pm4_queues.hh:258
gem5::GEM5_PACKED::reserved_80
uint32_t reserved_80
Definition: pm4_queues.hh:281
gem5::GEM5_PACKED::sdmax_rlcx_ib_offset
uint32_t sdmax_rlcx_ib_offset
Definition: pm4_queues.hh:213
gem5::GEM5_PACKED::reserved_64
uint32_t reserved_64
Definition: pm4_queues.hh:265
gem5::GEM5_PACKED::cp_hqd_ctx_save_control
uint32_t cp_hqd_ctx_save_control
Definition: pm4_queues.hh:170
gem5::GEM5_PACKED::reserved_93
uint32_t reserved_93
Definition: pm4_queues.hh:294
gem5::GEM5_PACKED::reserved_54
uint32_t reserved_54
Definition: pm4_queues.hh:255
gem5::PM4Queue::PM4Queue
PM4Queue(int id, QueueDesc *queue, Addr offset)
Definition: pm4_queues.hh:382
gem5::GEM5_PACKED::reserved_83
uint32_t reserved_83
Definition: pm4_queues.hh:284
gem5::GEM5_PACKED::reserved_92
uint32_t reserved_92
Definition: pm4_queues.hh:293
gem5::SDMAQueueDesc
struct gem5::GEM5_PACKED SDMAQueueDesc
Queue descriptor for SDMA-based user queues (RLC queues).
gem5::GEM5_PACKED::reserved_75
uint32_t reserved_75
Definition: pm4_queues.hh:276
gem5::GEM5_PACKED::cp_mqd_restore_end_time_hi
uint32_t cp_mqd_restore_end_time_hi
Definition: pm4_queues.hh:62
gem5::GEM5_PACKED::sdmax_rlcx_rb_aql_cntl
uint32_t sdmax_rlcx_rb_aql_cntl
Definition: pm4_queues.hh:231
gem5::GEM5_PACKED::cp_hqd_gds_resource_state
uint32_t cp_hqd_gds_resource_state
Definition: pm4_queues.hh:175
gem5::GEM5_PACKED::reserved_111
uint32_t reserved_111
Definition: pm4_queues.hh:312
gem5::GEM5_PACKED::hqd_pq_control
uint32_t hqd_pq_control
Definition: pm4_queues.hh:131
gem5::PM4Queue::ib
bool ib()
Definition: pm4_queues.hh:425
gem5::GEM5_PACKED::gds_cs_ctxsw_cnt0
uint32_t gds_cs_ctxsw_cnt0
Definition: pm4_queues.hh:65
gem5::GEM5_PACKED::reserved_60
uint32_t reserved_60
Definition: pm4_queues.hh:261
gem5::GEM5_PACKED::sdmax_rlcx_ib_cntl
uint32_t sdmax_rlcx_ib_cntl
Definition: pm4_queues.hh:211
gem5::GEM5_PACKED::reserved_84
uint32_t reserved_84
Definition: pm4_queues.hh:285
gem5::GEM5_PACKED::cp_hqd_ctx_save_size
uint32_t cp_hqd_ctx_save_size
Definition: pm4_queues.hh:174

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