gem5  v22.0.0.2
pm4_defines.hh
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32 
33 #ifndef __DEV_AMDGPU_PM4_DEFINES_H__
34 #define __DEV_AMDGPU_PM4_DEFINES_H__
35 
36 #include <cstdlib>
37 #include <iostream>
38 #include <vector>
39 
40 #include "base/types.hh"
41 
42 namespace gem5
43 {
44 
53 {
54  IT_NOP = 0x10,
55  IT_WRITE_DATA = 0x37,
63  IT_MAP_QUEUES = 0xA2,
66  IT_RUN_LIST = 0xA5,
67 };
68 
72 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
73 
77 typedef struct GEM5_PACKED
78 {
79  union
80  {
81  struct
82  {
83  uint16_t predicated : 1;
84  uint16_t shader : 1;
85  uint16_t reserved : 6;
86  uint16_t opcode : 8;
87  uint16_t count : 14;
88  uint16_t type : 2;
89  };
90  uint32_t ordinal;
91  };
92 } PM4Header;
93 static_assert(sizeof(PM4Header) == 4);
94 
95 typedef struct GEM5_PACKED
96 {
97  uint32_t reserved1 : 8;
98  uint32_t destSel : 4;
99  uint32_t reserved2 : 4;
100  uint32_t addrIncr : 1;
101  uint32_t reserved3 : 2;
102  uint32_t resume : 1;
103  uint32_t writeConfirm : 1;
104  uint32_t reserved4 : 4;
105  uint32_t cachePolicy : 2;
106  uint32_t reserved5 : 5;
107  union
108  {
109  struct
110  {
111  uint32_t destAddrLo;
112  uint32_t destAddrHi;
113  };
114  uint64_t destAddr;
115  };
116  uint32_t data;
117 } PM4WriteData;
118 static_assert(sizeof(PM4WriteData) == 16);
119 
120 typedef struct GEM5_PACKED
121 {
122  uint32_t reserved1 : 4;
123  uint32_t queueSel : 2;
124  uint32_t reserved2 : 2;
125  uint32_t vmid : 4;
126  uint32_t reserved3 : 1;
127  uint32_t me : 1;
128  uint32_t pipe : 2;
129  uint32_t queueSlot : 3;
130  uint32_t reserved6 : 2;
131  uint32_t queueType : 3;
132  uint32_t allocFormat : 2;
133  uint32_t engineSel : 3;
134  uint32_t numQueues : 3;
135  uint32_t reserved4 : 1;
136  uint32_t checkDisable : 1;
137  uint32_t doorbellOffset : 26;
138  uint32_t reserved5 : 4;
139  union
140  {
141  struct
142  {
143  uint32_t mqdAddrLo : 32;
144  uint32_t mqdAddrHi : 32;
145  };
146  uint64_t mqdAddr;
147  };
148  union
149  {
150  struct
151  {
152  uint32_t wptrAddrLo : 32;
153  uint32_t wptrAddrHi : 32;
154  };
155  uint64_t wptrAddr;
156  };
157 } PM4MapQueues;
158 static_assert(sizeof(PM4MapQueues) == 24);
159 
160 typedef struct GEM5_PACKED
161 {
162  uint32_t action : 2;
163  uint32_t reserved : 2;
164  uint32_t queueSel : 2;
165  uint32_t reserved1 : 20;
166  uint32_t engineSel : 3;
167  uint32_t numQueues : 3;
168  union
169  {
170  struct
171  {
172  uint32_t pasid : 16;
173  uint32_t reserved2 : 16;
174  };
175  struct
176  {
177  uint32_t reserved3 : 2;
178  uint32_t doorbellOffset0 : 26;
179  uint32_t reserved4 : 4;
180  };
181  };
182  uint32_t reserved5 : 2;
183  uint32_t doorbellOffset1 : 26;
184  uint32_t reserved6 : 4;
185  uint32_t reserved7 : 2;
186  uint32_t doorbellOffset2 : 26;
187  uint32_t reserved8 : 4;
188  uint32_t reserved9 : 2;
189  uint32_t doorbellOffset3 : 26;
190  uint32_t reserved10 : 4;
192 static_assert(sizeof(PM4UnmapQueues) == 20);
193 
194 typedef struct GEM5_PACKED
195 {
196  uint32_t vmidMask : 16;
197  uint32_t unmapLatency : 8;
198  uint32_t reserved : 5;
199  uint32_t queueType : 3;
200  union
201  {
202  struct
203  {
204  uint32_t queueMaskLo;
205  uint32_t queueMaskHi;
206  };
207  uint64_t queueMask;
208  };
209  union
210  {
211  struct
212  {
213  uint32_t gwsMaskLo;
214  uint32_t gwsMaskHi;
215  };
216  uint64_t gwsMask;
217  };
218  uint16_t oacMask;
219  uint16_t reserved1;
220  uint32_t gdsHeapBase : 6;
221  uint32_t reserved2 : 5;
222  uint32_t gdsHeapSize : 6;
223  uint32_t reserved3 : 15;
225 static_assert(sizeof(PM4SetResources) == 28);
226 
227 typedef struct GEM5_PACKED
228 {
229  uint32_t pasid : 16;
230  uint32_t reserved0 : 8;
231  uint32_t diq : 1;
232  uint32_t processQuantum : 7;
233  union
234  {
235  struct
236  {
237  uint32_t ptBaseLo;
238  uint32_t ptBaseHi;
239  };
240  uint64_t ptBase;
241  };
242  uint32_t shMemBases;
243  uint32_t shMemConfig;
244  uint32_t reserved1;
245  uint32_t reserved2;
246  uint32_t reserved3;
247  uint32_t reserved4;
248  uint32_t reserved5;
249  union
250  {
251  struct
252  {
253  uint32_t gdsAddrLo;
254  uint32_t gdsAddrHi;
255  };
256  uint64_t gdsAddr;
257  };
258  uint32_t numGws : 6;
259  uint32_t reserved7 : 2;
260  uint32_t numOac : 4;
261  uint32_t reserved8 : 4;
262  uint32_t gdsSize : 6;
263  uint32_t numQueues : 10;
264  union
265  {
266  struct
267  {
270  };
272  };
273 } PM4MapProcess;
274 static_assert(sizeof(PM4MapProcess) == 60);
275 
276 typedef struct GEM5_PACKED
277 {
278  uint32_t function : 4;
279  uint32_t memSpace : 2;
280  uint32_t operation : 2;
281  uint32_t reserved1 : 24;
282  union
283  {
284  struct
285  {
286  uint32_t regAddr1 : 18;
287  uint32_t reserved2 : 14;
288  };
289  uint32_t memAddrLo;
290  };
291  union
292  {
293  struct
294  {
295  uint32_t regAddr2 : 18;
296  uint32_t reserved3 : 14;
297  };
298  uint32_t memAddrHi;
299  };
300  uint32_t reference;
301  uint32_t mask;
302  uint32_t pollInterval;
303 } PM4WaitRegMem;
304 static_assert(sizeof(PM4WaitRegMem) == 24);
305 
306 typedef struct GEM5_PACKED
307 {
308  uint32_t regOffset : 16;
309  uint32_t reserved : 16;
310  uint32_t regData;
311 } PM4SetUConfig;
312 static_assert(sizeof(PM4SetUConfig) == 8);
313 
314 typedef struct GEM5_PACKED
315 {
316  union
317  {
318  struct
319  {
320  uint32_t ibBaseLo;
321  uint32_t ibBaseHi;
322  };
323  uint64_t ibBase;
324  };
325  uint32_t ibSize : 20;
326  uint32_t chain : 1;
327  uint32_t poll : 1;
328  uint32_t reserved0 : 1;
329  uint32_t valid: 1;
330  uint32_t vmid : 4;
331  uint32_t cachePolicy : 2;
332  uint32_t reserved1 : 1;
333  uint32_t priv : 1;
335 static_assert(sizeof(PM4IndirectBuf) == 12);
336 
337 typedef struct GEM5_PACKED
338 {
339  union
340  {
341  struct
342  {
343  uint32_t tmz : 1;
344  uint32_t reserved : 31;
345  };
346  uint32_t dummy;
347  };
348 } PM4SwitchBuf;
349 static_assert(sizeof(PM4SwitchBuf) == 4);
350 
351 typedef struct GEM5_PACKED
352 {
353  union
354  {
355  struct
356  {
357  uint32_t ibBaseLo;
358  uint32_t ibBaseHi;
359  };
360  uint64_t ibBase;
361  };
362  uint32_t ibSize : 20;
363  uint32_t chain : 1;
364  uint32_t ena : 1;
365  uint32_t reserved1 : 2;
366  uint32_t vmid : 4;
367  uint32_t cachePolicy : 2;
368  uint32_t preResume : 1;
369  uint32_t priv : 1;
371 static_assert(sizeof(PM4IndirectBufConst) == 12);
372 
373 typedef struct GEM5_PACKED
374 {
375  uint32_t tmz : 1;
376  uint32_t reserved : 27;
377  uint32_t command : 4;
378 } PM4FrameCtrl;
379 static_assert(sizeof(PM4FrameCtrl) == 4);
380 
381 typedef struct GEM5_PACKED
382 {
383  uint32_t event : 6;
384  uint32_t reserved0 : 2;
385  uint32_t eventIdx : 4;
386  uint32_t l1Volatile : 1;
387  uint32_t l2Volatile : 1;
388  uint32_t reserved1 : 1;
389  uint32_t l2WB : 1;
390  uint32_t l1Inv : 1;
391  uint32_t l2Inv : 1;
392  uint32_t reserved2 : 1;
393  uint32_t l2NC : 1;
394  uint32_t l2WC : 1;
395  uint32_t l2Meta : 1;
396  uint32_t reserved3 : 3;
397  uint32_t cachePolicy : 2;
398  uint32_t reserved4 : 1;
399  uint32_t execute : 1;
400  uint32_t reserved5 : 3;
401  uint32_t reserved6 : 16;
402  uint32_t destSelect : 2;
403  uint32_t reserved7 : 6;
404  uint32_t intSelect : 3;
405  uint32_t reserved8 : 2;
406  uint32_t dataSelect : 3;
407  union
408  {
409  struct
410  {
411  uint32_t addrLo;
412  uint32_t addrHi;
413  };
414  uint64_t addr;
415  };
416  union
417  {
418  struct
419  {
420  union
421  {
422  struct
423  {
424  uint32_t dwOffset : 16;
425  uint32_t numDws : 16;
426  };
427  uint32_t dataLo : 32;
428  };
429  uint32_t dataHi;
430  };
431  uint64_t data;
432  };
433  uint32_t intCtxId;
434 } PM4ReleaseMem;
435 static_assert(sizeof(PM4ReleaseMem) == 28);
436 
437 typedef struct GEM5_PACKED
438 {
439  uint32_t offset : 16;
440  uint32_t reserved : 16;
441  uint32_t data;
443 static_assert(sizeof(PM4SetUconfigReg) == 8);
444 
445 typedef struct GEM5_PACKED
446 {
447  union
448  {
449  struct
450  {
451  uint32_t ibBaseLo;
452  uint32_t ibBaseHi;
453  };
454  uint64_t ibBase;
455  };
456  uint32_t ibSize : 20;
457  uint32_t chain : 1;
458  uint32_t offleadPolling : 1;
459  uint32_t reserved1 : 1;
460  uint32_t valid : 1;
461  uint32_t processCnt : 4;
462  uint32_t reserved2 : 4;
463 } PM4RunList;
464 static_assert(sizeof(PM4RunList) == 12);
465 
466 typedef struct GEM5_PACKED
467 {
468  uint32_t contextId : 28;
469  uint32_t interruptSel : 2;
470  uint32_t command : 2;
471  union
472  {
473  struct
474  {
475  uint32_t pasid : 16;
476  uint32_t reserved0 : 16;
477  };
478  struct
479  {
480  uint32_t reserved1 : 2;
481  uint32_t doorbellOffset : 26;
482  uint32_t engineSel : 3;
483  uint32_t reserved2 : 1;
484  };
485  };
486  union
487  {
488  struct
489  {
490  uint32_t addrLo;
491  uint32_t addrHi;
492  };
493  uint64_t addr;
494  };
495  union
496  {
497  struct
498  {
499  uint32_t dataLo;
500  uint32_t dataHi;
501  };
502  uint64_t data;
503  };
505 static_assert(sizeof(PM4QueryStatus) == 24);
506 
507 } // namespace gem5
508 
509 #endif // __DEV_AMDGPU_PM4_DEFINES_HH__
gem5::GEM5_PACKED::ptBase
uint64_t ptBase
Definition: pm4_defines.hh:240
gem5::PM4RunList
struct gem5::GEM5_PACKED PM4RunList
gem5::GEM5_PACKED::mqdAddrHi
uint32_t mqdAddrHi
Definition: pm4_defines.hh:144
gem5::PM4QueryStatus
struct gem5::GEM5_PACKED PM4QueryStatus
gem5::PM4WriteData
struct gem5::GEM5_PACKED PM4WriteData
gem5::GEM5_PACKED::dummy
uint32_t dummy
Definition: pm4_defines.hh:346
gem5::IT_RUN_LIST
@ IT_RUN_LIST
Definition: pm4_defines.hh:66
gem5::GEM5_PACKED
PM4 packets.
Definition: pm4_defines.hh:77
gem5::IT_WAIT_REG_MEM
@ IT_WAIT_REG_MEM
Definition: pm4_defines.hh:56
gem5::GEM5_PACKED::doorbellOffset2
uint32_t doorbellOffset2
Definition: pm4_defines.hh:186
gem5::GEM5_PACKED::action
uint32_t action
Definition: pm4_defines.hh:162
gem5::GEM5_PACKED::mqdAddr
uint64_t mqdAddr
Definition: pm4_defines.hh:146
gem5::IT_INVALIDATE_TLBS
@ IT_INVALIDATE_TLBS
Definition: pm4_defines.hh:61
gem5::GEM5_PACKED::type
uint16_t type
Definition: pm4_defines.hh:88
gem5::GEM5_PACKED::operation
uint32_t operation
Definition: pm4_defines.hh:280
gem5::IT_INDIRECT_BUFFER
@ IT_INDIRECT_BUFFER
Definition: pm4_defines.hh:57
gem5::GEM5_PACKED::doorbellOffset1
uint32_t doorbellOffset1
Definition: pm4_defines.hh:183
gem5::GEM5_PACKED::preResume
uint32_t preResume
Definition: pm4_defines.hh:368
gem5::GEM5_PACKED::offleadPolling
uint32_t offleadPolling
Definition: pm4_defines.hh:458
gem5::PM4UnmapQueues
struct gem5::GEM5_PACKED PM4UnmapQueues
gem5::GEM5_PACKED::checkDisable
uint32_t checkDisable
Definition: pm4_defines.hh:136
gem5::GEM5_PACKED::execute
uint32_t execute
Definition: pm4_defines.hh:399
gem5::GEM5_PACKED::intSelect
uint32_t intSelect
Definition: pm4_defines.hh:404
gem5::GEM5_PACKED::reference
uint32_t reference
Definition: pm4_defines.hh:300
gem5::GEM5_PACKED::reserved1
uint32_t reserved1
Definition: pm4_defines.hh:97
gem5::GEM5_PACKED::destAddr
uint64_t destAddr
Definition: pm4_defines.hh:114
gem5::it_opcode_type
it_opcode_type
PM4 opcodes.
Definition: pm4_defines.hh:52
gem5::IT_QUERY_STATUS
@ IT_QUERY_STATUS
Definition: pm4_defines.hh:65
gem5::GEM5_PACKED::data
uint64_t data
Definition: pm4_defines.hh:431
gem5::GEM5_PACKED::ena
uint32_t ena
Definition: pm4_defines.hh:364
gem5::GEM5_PACKED::wptrAddrLo
uint32_t wptrAddrLo
Definition: pm4_defines.hh:152
gem5::GEM5_PACKED::regData
uint32_t regData
Definition: pm4_defines.hh:310
gem5::PM4SetUconfigReg
struct gem5::GEM5_PACKED PM4SetUconfigReg
gem5::IT_WRITE_DATA
@ IT_WRITE_DATA
Definition: pm4_defines.hh:55
gem5::GEM5_PACKED::reserved4
uint32_t reserved4
Definition: pm4_defines.hh:104
gem5::GEM5_PACKED::priv
uint32_t priv
Definition: pm4_defines.hh:333
gem5::GEM5_PACKED::poll
uint32_t poll
Definition: pm4_defines.hh:327
gem5::GEM5_PACKED::queueSel
uint32_t queueSel
Definition: pm4_defines.hh:123
gem5::GEM5_PACKED::reserved0
uint32_t reserved0
Definition: pm4_defines.hh:230
gem5::GEM5_PACKED::diq
uint32_t diq
Definition: pm4_defines.hh:231
gem5::GEM5_PACKED::reserved7
uint32_t reserved7
Definition: pm4_defines.hh:185
gem5::GEM5_PACKED::completionSignalLo
uint32_t completionSignalLo
Definition: pm4_defines.hh:268
gem5::IT_UNMAP_QUEUES
@ IT_UNMAP_QUEUES
Definition: pm4_defines.hh:64
gem5::GEM5_PACKED::ibBaseLo
uint32_t ibBaseLo
Definition: pm4_defines.hh:320
gem5::GEM5_PACKED::shMemConfig
uint32_t shMemConfig
Definition: pm4_defines.hh:243
gem5::PM4MapQueues
struct gem5::GEM5_PACKED PM4MapQueues
gem5::GEM5_PACKED::data
uint32_t data
Definition: pm4_defines.hh:116
gem5::GEM5_PACKED::vmidMask
uint32_t vmidMask
Definition: pm4_defines.hh:196
gem5::GEM5_PACKED::shMemBases
uint32_t shMemBases
Definition: pm4_defines.hh:242
gem5::GEM5_PACKED::unmapLatency
uint32_t unmapLatency
Definition: pm4_defines.hh:197
gem5::GEM5_PACKED::destAddrHi
uint32_t destAddrHi
Definition: pm4_defines.hh:112
gem5::GEM5_PACKED::wptrAddr
uint64_t wptrAddr
Definition: pm4_defines.hh:155
gem5::GEM5_PACKED::writeConfirm
uint32_t writeConfirm
Definition: pm4_defines.hh:103
gem5::GEM5_PACKED::doorbellOffset3
uint32_t doorbellOffset3
Definition: pm4_defines.hh:189
gem5::GEM5_PACKED::regOffset
uint32_t regOffset
Definition: pm4_defines.hh:308
gem5::GEM5_PACKED::dataLo
uint32_t dataLo
Definition: pm4_defines.hh:427
gem5::GEM5_PACKED::l2NC
uint32_t l2NC
Definition: pm4_defines.hh:393
gem5::IT_SWITCH_BUFFER
@ IT_SWITCH_BUFFER
Definition: pm4_defines.hh:60
gem5::PM4MapProcess
struct gem5::GEM5_PACKED PM4MapProcess
gem5::IT_RELEASE_MEM
@ IT_RELEASE_MEM
Definition: pm4_defines.hh:58
gem5::GEM5_PACKED::processQuantum
uint32_t processQuantum
Definition: pm4_defines.hh:232
gem5::PM4SwitchBuf
struct gem5::GEM5_PACKED PM4SwitchBuf
gem5::GEM5_PACKED::reserved3
uint32_t reserved3
Definition: pm4_defines.hh:101
gem5::GEM5_PACKED::queueType
uint32_t queueType
Definition: pm4_defines.hh:131
gem5::PM4SetResources
struct gem5::GEM5_PACKED PM4SetResources
gem5::GEM5_PACKED::wptrAddrHi
uint32_t wptrAddrHi
Definition: pm4_defines.hh:153
gem5::GEM5_PACKED::gdsAddr
uint64_t gdsAddr
Definition: pm4_defines.hh:256
gem5::GEM5_PACKED::command
uint32_t command
Definition: pm4_defines.hh:377
gem5::GEM5_PACKED::addrHi
uint32_t addrHi
Definition: pm4_defines.hh:412
gem5::GEM5_PACKED::memAddrHi
uint32_t memAddrHi
Definition: pm4_defines.hh:298
gem5::GEM5_PACKED::ptBaseLo
uint32_t ptBaseLo
Definition: pm4_defines.hh:237
gem5::GEM5_PACKED::mqdAddrLo
uint32_t mqdAddrLo
Definition: pm4_defines.hh:143
gem5::GEM5_PACKED::gwsMask
uint64_t gwsMask
Definition: pm4_defines.hh:216
gem5::GEM5_PACKED::dataSelect
uint32_t dataSelect
Definition: pm4_defines.hh:406
gem5::GEM5_PACKED::numGws
uint32_t numGws
Definition: pm4_defines.hh:258
gem5::GEM5_PACKED::addrLo
uint32_t addrLo
Definition: pm4_defines.hh:411
gem5::GEM5_PACKED::reserved9
uint32_t reserved9
Definition: pm4_defines.hh:188
gem5::GEM5_PACKED::resume
uint32_t resume
Definition: pm4_defines.hh:102
gem5::GEM5_PACKED::l2WC
uint32_t l2WC
Definition: pm4_defines.hh:394
gem5::GEM5_PACKED::reserved2
uint32_t reserved2
Definition: pm4_defines.hh:99
gem5::PM4FrameCtrl
struct gem5::GEM5_PACKED PM4FrameCtrl
gem5::GEM5_PACKED::pipe
uint32_t pipe
Definition: pm4_defines.hh:128
gem5::GEM5_PACKED::opcode
uint16_t opcode
Definition: pm4_defines.hh:86
gem5::GEM5_PACKED::doorbellOffset
uint32_t doorbellOffset
Definition: pm4_defines.hh:137
gem5::GEM5_PACKED::reserved5
uint32_t reserved5
Definition: pm4_defines.hh:106
gem5::GEM5_PACKED::regAddr1
uint32_t regAddr1
Definition: pm4_defines.hh:286
gem5::GEM5_PACKED::gdsAddrLo
uint32_t gdsAddrLo
Definition: pm4_defines.hh:253
gem5::GEM5_PACKED::predicated
uint16_t predicated
Definition: pm4_defines.hh:83
gem5::GEM5_PACKED::gwsMaskLo
uint32_t gwsMaskLo
Definition: pm4_defines.hh:213
gem5::GEM5_PACKED::valid
uint32_t valid
Definition: pm4_defines.hh:329
gem5::GEM5_PACKED::reserved10
uint32_t reserved10
Definition: pm4_defines.hh:190
gem5::GEM5_PACKED::gdsAddrHi
uint32_t gdsAddrHi
Definition: pm4_defines.hh:254
gem5::GEM5_PACKED::destAddrLo
uint32_t destAddrLo
Definition: pm4_defines.hh:111
gem5::GEM5_PACKED::doorbellOffset0
uint32_t doorbellOffset0
Definition: pm4_defines.hh:178
gem5::GEM5_PACKED::me
uint32_t me
Definition: pm4_defines.hh:127
gem5::GEM5_PACKED::event
uint32_t event
Definition: pm4_defines.hh:383
gem5::GEM5_PACKED::l1Inv
uint32_t l1Inv
Definition: pm4_defines.hh:390
gem5::GEM5_PACKED::addrIncr
uint32_t addrIncr
Definition: pm4_defines.hh:100
gem5::GEM5_PACKED::contextId
uint32_t contextId
Definition: pm4_defines.hh:468
gem5::GEM5_PACKED::function
uint32_t function
Definition: pm4_defines.hh:278
gem5::GEM5_PACKED::memAddrLo
uint32_t memAddrLo
Definition: pm4_defines.hh:289
gem5::PM4ReleaseMem
struct gem5::GEM5_PACKED PM4ReleaseMem
gem5::GEM5_PACKED::ptBaseHi
uint32_t ptBaseHi
Definition: pm4_defines.hh:238
gem5::IT_MAP_QUEUES
@ IT_MAP_QUEUES
Definition: pm4_defines.hh:63
gem5::GEM5_PACKED::ordinal
uint32_t ordinal
Definition: pm4_defines.hh:90
gem5::GEM5_PACKED::queueSlot
uint32_t queueSlot
Definition: pm4_defines.hh:129
gem5::GEM5_PACKED::cachePolicy
uint32_t cachePolicy
Definition: pm4_defines.hh:105
gem5::GEM5_PACKED::reserved6
uint32_t reserved6
Definition: pm4_defines.hh:130
gem5::GEM5_PACKED::completionSignalHi
uint32_t completionSignalHi
Definition: pm4_defines.hh:269
gem5::PM4IndirectBuf
struct gem5::GEM5_PACKED PM4IndirectBuf
gem5::PM4IndirectBufConst
struct gem5::GEM5_PACKED PM4IndirectBufConst
gem5::PM4SetUConfig
struct gem5::GEM5_PACKED PM4SetUConfig
gem5::GEM5_PACKED::ibBase
uint64_t ibBase
Definition: pm4_defines.hh:323
gem5::GEM5_PACKED::ibBaseHi
uint32_t ibBaseHi
Definition: pm4_defines.hh:321
gem5::GEM5_PACKED::numOac
uint32_t numOac
Definition: pm4_defines.hh:260
gem5::GEM5_PACKED::pollInterval
uint32_t pollInterval
Definition: pm4_defines.hh:302
gem5::GEM5_PACKED::shader
uint16_t shader
Definition: pm4_defines.hh:84
gem5::IT_MAP_PROCESS
@ IT_MAP_PROCESS
Definition: pm4_defines.hh:62
gem5::GEM5_PACKED::destSel
uint32_t destSel
Definition: pm4_defines.hh:98
types.hh
gem5::GEM5_PACKED::gdsHeapSize
uint32_t gdsHeapSize
Definition: pm4_defines.hh:222
gem5::GEM5_PACKED::engineSel
uint32_t engineSel
Definition: pm4_defines.hh:133
gem5::GEM5_PACKED::offset
uint32_t offset
Definition: pm4_defines.hh:439
gem5::GEM5_PACKED::reserved
uint32_t reserved
Definition: pm4_defines.hh:163
gem5::GEM5_PACKED::chain
uint32_t chain
Definition: pm4_defines.hh:326
gem5::GEM5_PACKED::gdsSize
uint32_t gdsSize
Definition: pm4_defines.hh:262
gem5::GEM5_PACKED::addr
uint64_t addr
Definition: pm4_defines.hh:414
gem5::GEM5_PACKED::queueMaskHi
uint32_t queueMaskHi
Definition: pm4_defines.hh:205
gem5::GEM5_PACKED::queueMaskLo
uint32_t queueMaskLo
Definition: pm4_defines.hh:204
gem5::GEM5_PACKED::dataHi
uint32_t dataHi
Definition: pm4_defines.hh:429
gem5::GEM5_PACKED::pasid
uint32_t pasid
Definition: pm4_defines.hh:172
gem5::GEM5_PACKED::queueMask
uint64_t queueMask
Definition: pm4_defines.hh:207
gem5::GEM5_PACKED::l2WB
uint32_t l2WB
Definition: pm4_defines.hh:389
gem5::PM4Header
struct gem5::GEM5_PACKED PM4Header
PM4 packets.
gem5::GEM5_PACKED::numDws
uint32_t numDws
Definition: pm4_defines.hh:425
gem5::GEM5_PACKED::vmid
uint32_t vmid
Definition: pm4_defines.hh:125
gem5::GEM5_PACKED::reserved8
uint32_t reserved8
Definition: pm4_defines.hh:187
gem5::GEM5_PACKED::mask
uint32_t mask
Definition: pm4_defines.hh:301
gem5::IT_NOP
@ IT_NOP
Definition: pm4_defines.hh:54
gem5::GEM5_PACKED::l1Volatile
uint32_t l1Volatile
Definition: pm4_defines.hh:386
gem5::GEM5_PACKED::gdsHeapBase
uint32_t gdsHeapBase
Definition: pm4_defines.hh:220
gem5::GEM5_PACKED::processCnt
uint32_t processCnt
Definition: pm4_defines.hh:461
gem5::GEM5_PACKED::memSpace
uint32_t memSpace
Definition: pm4_defines.hh:279
gem5::GEM5_PACKED::ibSize
uint32_t ibSize
Definition: pm4_defines.hh:325
gem5::GEM5_PACKED::count
uint16_t count
Definition: pm4_defines.hh:87
gem5::GEM5_PACKED::reserved
uint16_t reserved
Definition: pm4_defines.hh:85
gem5::GEM5_PACKED::allocFormat
uint32_t allocFormat
Definition: pm4_defines.hh:132
gem5::GEM5_PACKED::interruptSel
uint32_t interruptSel
Definition: pm4_defines.hh:469
gem5::GEM5_PACKED::l2Meta
uint32_t l2Meta
Definition: pm4_defines.hh:395
gem5::GEM5_PACKED::numQueues
uint32_t numQueues
Definition: pm4_defines.hh:134
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GEM5_PACKED::gwsMaskHi
uint32_t gwsMaskHi
Definition: pm4_defines.hh:214
gem5::GEM5_PACKED::eventIdx
uint32_t eventIdx
Definition: pm4_defines.hh:385
gem5::IT_SET_UCONFIG_REG
@ IT_SET_UCONFIG_REG
Definition: pm4_defines.hh:59
gem5::GEM5_PACKED::oacMask
uint16_t oacMask
Definition: pm4_defines.hh:218
gem5::GEM5_PACKED::completionSignal
uint64_t completionSignal
Definition: pm4_defines.hh:271
gem5::PM4WaitRegMem
struct gem5::GEM5_PACKED PM4WaitRegMem
gem5::GEM5_PACKED::dwOffset
uint32_t dwOffset
Definition: pm4_defines.hh:424
gem5::GEM5_PACKED::l2Volatile
uint32_t l2Volatile
Definition: pm4_defines.hh:387
gem5::GEM5_PACKED::destSelect
uint32_t destSelect
Definition: pm4_defines.hh:402
gem5::GEM5_PACKED::regAddr2
uint32_t regAddr2
Definition: pm4_defines.hh:295
gem5::GEM5_PACKED::tmz
uint32_t tmz
Definition: pm4_defines.hh:343
gem5::GEM5_PACKED::l2Inv
uint32_t l2Inv
Definition: pm4_defines.hh:391
gem5::GEM5_PACKED::intCtxId
uint32_t intCtxId
Definition: pm4_defines.hh:433
gem5::GEM5_PACKED::reserved1
uint16_t reserved1
Definition: pm4_defines.hh:219

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