gem5  v22.0.0.2
pagetable.hh
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31 
32 #ifndef __ARCH_POWER_PAGETABLE_H__
33 #define __ARCH_POWER_PAGETABLE_H__
34 
35 #include "base/types.hh"
36 #include "sim/serialize.hh"
37 
38 namespace gem5
39 {
40 
41 namespace PowerISA
42 {
43 
44 // ITB/DTB page table entry
45 struct PTE
46 {
47  // What parts of the VAddr (from bits 28..11) should be used in
48  // translation (includes Mask and MaskX from PageMask)
50 
51  // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11
52  // from EntryHi)
54 
55  // Address Space ID (8 bits) // Lower 8 bits of EntryHi
56  uint8_t asid;
57 
58  // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
59  bool G;
60 
61  /* Contents of Entry Lo0 */
62  Addr PFN0; // Physical Frame Number - Even
63  bool D0; // Even entry Dirty Bit
64  bool V0; // Even entry Valid Bit
65  uint8_t C0; // Cache Coherency Bits - Even
66 
67  /* Contents of Entry Lo1 */
68  Addr PFN1; // Physical Frame Number - Odd
69  bool D1; // Odd entry Dirty Bit
70  bool V1; // Odd entry Valid Bit
71  uint8_t C1; // Cache Coherency Bits (3 bits)
72 
73  // The next few variables are put in as optimizations to reduce TLB
74  // lookup overheads. For a given Mask, what is the address shift amount
75  // and what is the OffsetMask
78 
79  bool
81  {
82  return (V0 | V1);
83  };
84 
85  void serialize(CheckpointOut &cp) const;
86  void unserialize(CheckpointIn &cp);
87 };
88 
89 } // namespace PowerISA
90 } // namespace gem5
91 
92 #endif // __ARCH_POWER_PAGETABLE_H__
gem5::PowerISA::PTE::V0
bool V0
Definition: pagetable.hh:64
gem5::PowerISA::PTE::VPN
Addr VPN
Definition: pagetable.hh:53
gem5::PowerISA::PTE::asid
uint8_t asid
Definition: pagetable.hh:56
gem5::PowerISA::PTE::Valid
bool Valid()
Definition: pagetable.hh:80
serialize.hh
gem5::PowerISA::PTE::C0
uint8_t C0
Definition: pagetable.hh:65
gem5::PowerISA::PTE::AddrShiftAmount
int AddrShiftAmount
Definition: pagetable.hh:76
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::PowerISA::PTE::PFN0
Addr PFN0
Definition: pagetable.hh:62
gem5::PowerISA::PTE::OffsetMask
int OffsetMask
Definition: pagetable.hh:77
gem5::PowerISA::PTE::serialize
void serialize(CheckpointOut &cp) const
Definition: pagetable.cc:43
gem5::PowerISA::PTE::unserialize
void unserialize(CheckpointIn &cp)
Definition: pagetable.cc:62
gem5::PowerISA::PTE::G
bool G
Definition: pagetable.hh:59
gem5::PowerISA::PTE::D0
bool D0
Definition: pagetable.hh:63
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::PTE::D1
bool D1
Definition: pagetable.hh:69
gem5::PowerISA::PTE::Mask
Addr Mask
Definition: pagetable.hh:49
types.hh
gem5::PowerISA::PTE::V1
bool V1
Definition: pagetable.hh:70
gem5::PowerISA::PTE::PFN1
Addr PFN1
Definition: pagetable.hh:68
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::PowerISA::PTE
Definition: pagetable.hh:45
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PowerISA::PTE::C1
uint8_t C1
Definition: pagetable.hh:71

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