gem5  v21.2.1.1
sc_signal_resolved.cc
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27 
28 #include "systemc/core/process.hh"
31 #include "systemc/ext/core/sc_module.hh" // for sc_gen_unique_name
32 
33 namespace sc_core
34 {
35 
37  sc_signal<sc_dt::sc_logic, SC_MANY_WRITERS>(
38  sc_gen_unique_name("signal_resolved"))
39 {}
40 
43 {}
44 
47 
48 void
50 {
52 
53  auto it = inputs.find(p);
54  if (it == inputs.end()) {
55  inputs.emplace(p, l);
57  } else if (it->second != l) {
58  it->second = l;
60  }
61 }
62 
65 {
66  write(l);
67  return *this;
68 }
69 
72 {
73  write(r.read());
74  return *this;
75 }
76 
77 void
79 {
80  using sc_dt::Log_0;
81  using sc_dt::Log_1;
82  using sc_dt::Log_Z;
83  using sc_dt::Log_X;
84  static sc_dt::sc_logic_value_t merge_table[4][4] = {
85  { Log_0, Log_X, Log_0, Log_X },
86  { Log_X, Log_1, Log_1, Log_X },
87  { Log_0, Log_1, Log_Z, Log_X },
88  { Log_X, Log_X, Log_X, Log_X }
89  };
90 
91  // Resolve the inputs, and give the result to the underlying signal class.
92  m_new_val = Log_Z;
93  for (auto &input: inputs)
94  m_new_val = merge_table[m_new_val.value()][input.second.value()];
95 
96  // Ask the signal to update it's value.
98 }
99 
100 } // namespace sc_core
sc_core::sc_port_base
Definition: sc_port.hh:74
sc_dt
Definition: sc_bit.cc:67
sc_core::sc_signal_resolved::sc_signal_resolved
sc_signal_resolved()
Definition: sc_signal_resolved.cc:36
sc_core
Definition: messages.cc:31
sc_dt::sc_logic::value
sc_logic_value_t value() const
Definition: sc_logic.hh:268
sc_core::sc_interface
Definition: sc_interface.hh:37
sc_core::sc_signal
Definition: sc_signal.hh:272
sc_dt::sc_logic
Definition: sc_logic.hh:130
sc_core::sc_prim_channel::request_update
void request_update()
Definition: sc_prim.cc:70
sc_dt::sc_logic_value_t
sc_logic_value_t
Definition: sc_logic.hh:116
sc_core::sc_signal_resolved::register_port
virtual void register_port(sc_port_base &, const char *)
Definition: sc_signal_resolved.cc:46
sc_core::SC_MANY_WRITERS
@ SC_MANY_WRITERS
Definition: sc_signal_inout_if.hh:40
sc_core::sc_signal_resolved::operator=
sc_signal_resolved & operator=(const sc_dt::sc_logic &)
Definition: sc_signal_resolved.cc:64
sc_core::sc_signal_resolved::update
virtual void update()
Definition: sc_signal_resolved.cc:78
sc_dt::Log_Z
@ Log_Z
Definition: sc_logic.hh:120
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
sc_signal_resolved.hh
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
sc_core::sc_gen_unique_name
const char * sc_gen_unique_name(const char *seed)
Definition: sc_module.cc:820
sc_gem5::Process
Definition: process.hh:62
sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::m_new_val
sc_dt::sc_logic m_new_val
Definition: sc_signal.hh:236
name
const std::string & name()
Definition: trace.cc:49
sc_module.hh
process.hh
sc_core::sc_signal_resolved
Definition: sc_signal_resolved.hh:55
sc_gem5::Scheduler::current
Process * current()
Definition: scheduler.hh:185
sc_core::sc_signal::update
virtual void update()
Definition: sc_signal.hh:301
sc_dt::Log_X
@ Log_X
Definition: sc_logic.hh:121
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
sc_gem5::scheduler
Scheduler scheduler
Definition: scheduler.cc:494
sc_core::sc_signal_resolved::~sc_signal_resolved
virtual ~sc_signal_resolved()
Definition: sc_signal_resolved.cc:45
sc_dt::Log_0
@ Log_0
Definition: sc_logic.hh:118
sc_dt::Log_1
@ Log_1
Definition: sc_logic.hh:119
sc_core::sc_signal_resolved::write
virtual void write(const sc_dt::sc_logic &)
Definition: sc_signal_resolved.cc:49
sc_core::sc_signal_resolved::inputs
std::map<::sc_gem5::Process *, sc_dt::sc_logic > inputs
Definition: sc_signal_resolved.hh:79
scheduler.hh

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