gem5
v24.1.0.1
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systemc
channel
sc_signal_resolved.cc
Go to the documentation of this file.
1
/*
2
* Copyright 2018 Google, Inc.
3
*
4
* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions are
6
* met: redistributions of source code must retain the above copyright
7
* notice, this list of conditions and the following disclaimer;
8
* redistributions in binary form must reproduce the above copyright
9
* notice, this list of conditions and the following disclaimer in the
10
* documentation and/or other materials provided with the distribution;
11
* neither the name of the copyright holders nor the names of its
12
* contributors may be used to endorse or promote products derived from
13
* this software without specific prior written permission.
14
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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28
#include "
systemc/core/process.hh
"
29
#include "
systemc/core/scheduler.hh
"
30
#include "
systemc/ext/channel/sc_signal_resolved.hh
"
31
#include "
systemc/ext/core/sc_module.hh
"
// for sc_gen_unique_name
32
33
namespace
sc_core
34
{
35
36
sc_signal_resolved::sc_signal_resolved
() :
sc_interface
(),
37
sc_signal
<
sc_dt
::sc_logic,
SC_MANY_WRITERS
>(
38
sc_gen_unique_name
(
"signal_resolved"
))
39
{}
36
sc_signal_resolved::sc_signal_resolved
() :
sc_interface
(), {
…
}
40
41
sc_signal_resolved::sc_signal_resolved
(
const
char
*
name
) :
42
sc_interface
(),
sc_signal
<
sc_dt
::sc_logic,
SC_MANY_WRITERS
>(
name
)
43
{}
41
sc_signal_resolved::sc_signal_resolved
(
const
char
*
name
) : {
…
}
44
45
sc_signal_resolved::~sc_signal_resolved
() {}
46
void
sc_signal_resolved::register_port
(
sc_port_base
&,
const
char
*) {}
47
48
void
49
sc_signal_resolved::write
(
const
sc_dt::sc_logic
&l)
50
{
51
::sc_gem5::Process
*p =
::sc_gem5::scheduler
.
current
();
52
53
auto
it =
inputs
.find(p);
54
if
(it ==
inputs
.end()) {
55
inputs
.emplace(p, l);
56
request_update
();
57
}
else
if
(it->second != l) {
58
it->second = l;
59
request_update
();
60
}
61
}
49
sc_signal_resolved::write
(
const
sc_dt::sc_logic
&l) {
…
}
62
63
sc_signal_resolved
&
64
sc_signal_resolved::operator =
(
const
sc_dt::sc_logic
&l)
65
{
66
write
(l);
67
return
*
this
;
68
}
64
sc_signal_resolved::operator =
(
const
sc_dt::sc_logic
&l) {
…
}
69
70
sc_signal_resolved
&
71
sc_signal_resolved::operator =
(
const
sc_signal_resolved
&r)
72
{
73
write
(r.read());
74
return
*
this
;
75
}
71
sc_signal_resolved::operator =
(
const
sc_signal_resolved
&r) {
…
}
76
77
void
78
sc_signal_resolved::update
()
79
{
80
using
sc_dt::Log_0
;
81
using
sc_dt::Log_1
;
82
using
sc_dt::Log_Z
;
83
using
sc_dt::Log_X
;
84
static
sc_dt::sc_logic_value_t
merge_table[4][4] = {
85
{ Log_0, Log_X, Log_0, Log_X },
86
{ Log_X, Log_1, Log_1, Log_X },
87
{ Log_0, Log_1, Log_Z, Log_X },
88
{ Log_X, Log_X, Log_X, Log_X }
89
};
90
91
// Resolve the inputs, and give the result to the underlying signal class.
92
m_new_val
= Log_Z;
93
for
(
auto
&input:
inputs
)
94
m_new_val
= merge_table[
m_new_val
.value()][input.second.value()];
95
96
// Ask the signal to update it's value.
97
sc_signal<sc_dt::sc_logic, SC_MANY_WRITERS>::update
();
98
}
78
sc_signal_resolved::update
() {
…
}
99
100
}
// namespace sc_core
sc_core::sc_interface
Definition
sc_interface.hh:38
sc_core::sc_port_base
Definition
sc_port.hh:75
sc_core::sc_prim_channel::request_update
void request_update()
Definition
sc_prim.cc:70
sc_core::sc_signal_resolved
Definition
sc_signal_resolved.hh:56
sc_core::sc_signal_resolved::sc_signal_resolved
sc_signal_resolved()
Definition
sc_signal_resolved.cc:36
sc_core::sc_signal_resolved::~sc_signal_resolved
virtual ~sc_signal_resolved()
Definition
sc_signal_resolved.cc:45
sc_core::sc_signal_resolved::write
virtual void write(const sc_dt::sc_logic &)
Definition
sc_signal_resolved.cc:49
sc_core::sc_signal_resolved::operator=
sc_signal_resolved & operator=(const sc_dt::sc_logic &)
Definition
sc_signal_resolved.cc:64
sc_core::sc_signal_resolved::register_port
virtual void register_port(sc_port_base &, const char *)
Definition
sc_signal_resolved.cc:46
sc_core::sc_signal_resolved::update
virtual void update()
Definition
sc_signal_resolved.cc:78
sc_core::sc_signal_resolved::inputs
std::map<::sc_gem5::Process *, sc_dt::sc_logic > inputs
Definition
sc_signal_resolved.hh:79
sc_core::sc_signal
Definition
sc_signal.hh:273
sc_core::sc_signal::update
virtual void update()
Definition
sc_signal.hh:301
sc_dt::sc_logic
Definition
sc_logic.hh:99
sc_gem5::Process
Definition
process.hh:63
sc_gem5::ScSignalBaseT::m_new_val
T m_new_val
Definition
sc_signal.hh:236
sc_gem5::Scheduler::current
Process * current()
Definition
scheduler.hh:185
sc_core
Definition
messages.cc:32
sc_core::sc_gen_unique_name
const char * sc_gen_unique_name(const char *seed)
Definition
sc_module.cc:820
sc_core::SC_MANY_WRITERS
@ SC_MANY_WRITERS
Definition
sc_signal_inout_if.hh:40
sc_dt
Definition
sc_bit.cc:68
sc_dt::sc_logic_value_t
sc_logic_value_t
Definition
sc_logic.hh:85
sc_dt::Log_Z
@ Log_Z
Definition
sc_logic.hh:88
sc_dt::Log_1
@ Log_1
Definition
sc_logic.hh:87
sc_dt::Log_X
@ Log_X
Definition
sc_logic.hh:89
sc_dt::Log_0
@ Log_0
Definition
sc_logic.hh:86
sc_gem5::scheduler
Scheduler scheduler
Definition
scheduler.cc:494
sc_module.hh
sc_signal_resolved.hh
process.hh
scheduler.hh
name
const std::string & name()
Definition
trace.cc:48
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