gem5 v24.0.0.0
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sc_signal_resolved.hh
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1/*
2 * Copyright 2018 Google, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 */
27
28#ifndef __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RESOLVED_HH__
29#define __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RESOLVED_HH__
30
31#include <map>
32
33#include "sc_signal.hh"
34#include "sc_signal_inout_if.hh"
35
36namespace sc_dt
37{
38
39class sc_logic;
40
41};
42
43namespace sc_gem5
44{
45
46class Process;
47
48} // namespace sc_gem5
49
50namespace sc_core
51{
52
53class sc_port_base;
54
55class sc_signal_resolved : public sc_signal<sc_dt::sc_logic, SC_MANY_WRITERS>
56{
57 public:
59 explicit sc_signal_resolved(const char *name);
60 virtual ~sc_signal_resolved();
61
62 virtual void register_port(sc_port_base &, const char *);
63
64 virtual void write(const sc_dt::sc_logic &);
67
68 virtual const char *kind() const { return "sc_signal_resolved"; }
69
70 protected:
71 virtual void update();
72
73 private:
74 // Disabled
76 sc_interface(), sc_signal<sc_dt::sc_logic, SC_MANY_WRITERS>()
77 {}
78
79 std::map<::sc_gem5::Process *, sc_dt::sc_logic> inputs;
80};
81
82} // namespace sc_core
83
84#endif //__SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RESOLVED_HH__
virtual void write(const sc_dt::sc_logic &)
sc_signal_resolved & operator=(const sc_dt::sc_logic &)
virtual const char * kind() const
sc_signal_resolved(const sc_signal_resolved &)
virtual void register_port(sc_port_base &, const char *)
std::map<::sc_gem5::Process *, sc_dt::sc_logic > inputs
const std::string & name()
Definition trace.cc:48

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