gem5  v22.0.0.1
Classes | Namespaces | Enumerations
smmu_v3_defs.hh File Reference
#include <stdint.h>
#include "base/bitunion.hh"

Go to the source code of this file.

Classes

union  gem5::SMMURegs
 
struct  gem5::StreamTableEntry
 
struct  gem5::ContextDescriptor
 
struct  gem5::SMMUCommand
 
struct  gem5::SMMUEvent
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 

Enumerations

enum  { gem5::SMMU_SECURE_SZ = 0x184, gem5::SMMU_PAGE_ZERO_SZ = 0x10000, gem5::SMMU_PAGE_ONE_SZ = 0x10000, gem5::SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ }
 
enum  {
  gem5::STE_CONFIG_ABORT = 0x0, gem5::STE_CONFIG_BYPASS = 0x4, gem5::STE_CONFIG_STAGE1_ONLY = 0x5, gem5::STE_CONFIG_STAGE2_ONLY = 0x6,
  gem5::STE_CONFIG_STAGE1_AND_2 = 0x7
}
 
enum  { gem5::STAGE1_CFG_1L = 0x0, gem5::STAGE1_CFG_2L_4K = 0x1, gem5::STAGE1_CFG_2L_64K = 0x2 }
 
enum  { gem5::ST_CFG_SPLIT_SHIFT = 6, gem5::ST_CD_ADDR_SHIFT = 6, gem5::CD_TTB_SHIFT = 4, gem5::STE_S2TTB_SHIFT = 4 }
 
enum  { gem5::TRANS_GRANULE_4K = 0x0, gem5::TRANS_GRANULE_64K = 0x1, gem5::TRANS_GRANULE_16K = 0x2, gem5::TRANS_GRANULE_INVALID = 0x3 }
 
enum  {
  gem5::ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, gem5::ST_CFG_SIZE_MASK = 0x000000000000003fULL, gem5::ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL, gem5::ST_CFG_FMT_MASK = 0x0000000000030000ULL,
  gem5::ST_CFG_FMT_LINEAR = 0x0000000000000000ULL, gem5::ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL, gem5::ST_L2_SPAN_MASK = 0x000000000000001fULL, gem5::ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
  gem5::VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, gem5::VMT_BASE_SIZE_MASK = 0x000000000000001fULL, gem5::Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, gem5::Q_BASE_SIZE_MASK = 0x000000000000001fULL,
  gem5::E_BASE_ENABLE_MASK = 0x8000000000000000ULL, gem5::E_BASE_ADDR_MASK = 0x0000fffffffffffcULL
}
 
enum  {
  gem5::CR0_SMMUEN_MASK = 0x1, gem5::CR0_PRIQEN_MASK = 0x2, gem5::CR0_EVENTQEN_MASK = 0x4, gem5::CR0_CMDQEN_MASK = 0x8,
  gem5::CR0_ATSCHK_MASK = 0x10, gem5::CR0_VMW_MASK = 0x1C0
}
 
enum  gem5::SMMUCommandType {
  gem5::CMD_PRF_CONFIG = 0x01, gem5::CMD_PRF_ADDR = 0x02, gem5::CMD_CFGI_STE = 0x03, gem5::CMD_CFGI_STE_RANGE = 0x04,
  gem5::CMD_CFGI_CD = 0x05, gem5::CMD_CFGI_CD_ALL = 0x06, gem5::CMD_TLBI_NH_ALL = 0x10, gem5::CMD_TLBI_NH_ASID = 0x11,
  gem5::CMD_TLBI_NH_VAA = 0x13, gem5::CMD_TLBI_NH_VA = 0x12, gem5::CMD_TLBI_EL3_ALL = 0x18, gem5::CMD_TLBI_EL3_VA = 0x1A,
  gem5::CMD_TLBI_EL2_ALL = 0x20, gem5::CMD_TLBI_EL2_ASID = 0x21, gem5::CMD_TLBI_EL2_VA = 0x22, gem5::CMD_TLBI_EL2_VAA = 0x23,
  gem5::CMD_TLBI_S2_IPA = 0x2a, gem5::CMD_TLBI_S12_VMALL = 0x28, gem5::CMD_TLBI_NSNH_ALL = 0x30, gem5::CMD_ATC_INV = 0x40,
  gem5::CMD_PRI_RESP = 0x41, gem5::CMD_RESUME = 0x44, gem5::CMD_STALL_TERM = 0x45, gem5::CMD_SYNC = 0x46
}
 
enum  gem5::SMMUEventTypes { gem5::EVT_FAULT = 0x0001 }
 
enum  gem5::SMMUEventFlags { gem5::EVF_WRITE = 0x0001 }
 
enum  { gem5::SMMU_MAX_TRANS_ID = 64 }
 

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