#include <smmu_v3_defs.hh>
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| t0sz |
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Bitfield< 7, 6 > | tg0 |
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Bitfield< 9, 8 > | ir0 |
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Bitfield< 11, 10 > | or0 |
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Bitfield< 13, 12 > | sh0 |
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Bitfield< 14 > | epd0 |
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Bitfield< 15 > | endi |
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Bitfield< 21, 16 > | t1sz |
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Bitfield< 23, 22 > | tg1 |
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Bitfield< 25, 24 > | ir1 |
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Bitfield< 27, 26 > | or1 |
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Bitfield< 29, 28 > | sh1 |
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Bitfield< 30 > | epd1 |
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Bitfield< 31 > | valid |
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Bitfield< 34, 32 > | ips |
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Bitfield< 35 > | affd |
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Bitfield< 36 > | wxn |
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Bitfield< 37 > | uwxn |
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Bitfield< 39, 38 > | tbi |
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Bitfield< 40 > | pan |
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Bitfield< 41 > | aa64 |
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Bitfield< 42 > | hd |
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Bitfield< 43 > | ha |
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Bitfield< 44 > | s |
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Bitfield< 45 > | r |
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Bitfield< 46 > | a |
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Bitfield< 47 > | aset |
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Bitfield< 63, 48 > | asid |
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Bitfield< 1 > | had0 |
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Bitfield< 51, 4 > | ttb0 |
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Bitfield< 60 > | hwu0g59 |
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Bitfield< 61 > | hwu0g60 |
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Bitfield< 62 > | hwu0g61 |
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Bitfield< 63 > | hwu0g62 |
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Bitfield< 1 > | had1 |
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Bitfield< 51, 4 > | ttb1 |
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Bitfield< 60 > | hwu1g59 |
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Bitfield< 61 > | hwu1g60 |
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Bitfield< 62 > | hwu1g61 |
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Bitfield< 63 > | hwu1g62 |
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uint64_t | mair |
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uint64_t | amair |
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uint64_t | _pad [3] |
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Definition at line 292 of file smmu_v3_defs.hh.
◆ BitUnion64() [1/3]
gem5::ContextDescriptor::BitUnion64 |
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DWORD0 | | ) |
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◆ BitUnion64() [2/3]
gem5::ContextDescriptor::BitUnion64 |
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DWORD1 | | ) |
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◆ BitUnion64() [3/3]
gem5::ContextDescriptor::BitUnion64 |
( |
DWORD2 | | ) |
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◆ EndBitUnion() [1/3]
gem5::ContextDescriptor::EndBitUnion |
( |
DWORD0 | | ) |
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◆ EndBitUnion() [2/3]
gem5::ContextDescriptor::EndBitUnion |
( |
DWORD1 | | ) |
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◆ EndBitUnion() [3/3]
gem5::ContextDescriptor::EndBitUnion |
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DWORD2 | | ) |
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◆ _pad
uint64_t gem5::ContextDescriptor::_pad[3] |
Bitfield<46> gem5::ContextDescriptor::a |
◆ aa64
Bitfield<41> gem5::ContextDescriptor::aa64 |
◆ affd
Bitfield<35> gem5::ContextDescriptor::affd |
◆ amair
uint64_t gem5::ContextDescriptor::amair |
◆ aset
Bitfield<47> gem5::ContextDescriptor::aset |
◆ asid
Bitfield<63, 48> gem5::ContextDescriptor::asid |
◆ endi
Bitfield<15> gem5::ContextDescriptor::endi |
◆ epd0
Bitfield<14> gem5::ContextDescriptor::epd0 |
◆ epd1
Bitfield<30> gem5::ContextDescriptor::epd1 |
◆ ha
Bitfield<43> gem5::ContextDescriptor::ha |
◆ had0
Bitfield<1> gem5::ContextDescriptor::had0 |
◆ had1
Bitfield<1> gem5::ContextDescriptor::had1 |
◆ hd
Bitfield<42> gem5::ContextDescriptor::hd |
◆ hwu0g59
Bitfield<60> gem5::ContextDescriptor::hwu0g59 |
◆ hwu0g60
Bitfield<61> gem5::ContextDescriptor::hwu0g60 |
◆ hwu0g61
Bitfield<62> gem5::ContextDescriptor::hwu0g61 |
◆ hwu0g62
Bitfield<63> gem5::ContextDescriptor::hwu0g62 |
◆ hwu1g59
Bitfield<60> gem5::ContextDescriptor::hwu1g59 |
◆ hwu1g60
Bitfield<61> gem5::ContextDescriptor::hwu1g60 |
◆ hwu1g61
Bitfield<62> gem5::ContextDescriptor::hwu1g61 |
◆ hwu1g62
Bitfield<63> gem5::ContextDescriptor::hwu1g62 |
◆ ips
Bitfield<34, 32> gem5::ContextDescriptor::ips |
◆ ir0
Bitfield<9, 8> gem5::ContextDescriptor::ir0 |
◆ ir1
Bitfield<25, 24> gem5::ContextDescriptor::ir1 |
◆ mair
uint64_t gem5::ContextDescriptor::mair |
◆ or0
Bitfield<11, 10> gem5::ContextDescriptor::or0 |
◆ or1
Bitfield<27, 26> gem5::ContextDescriptor::or1 |
◆ pan
Bitfield<40> gem5::ContextDescriptor::pan |
Bitfield<45> gem5::ContextDescriptor::r |
Bitfield<44> gem5::ContextDescriptor::s |
◆ sh0
Bitfield<13, 12> gem5::ContextDescriptor::sh0 |
◆ sh1
Bitfield<29, 28> gem5::ContextDescriptor::sh1 |
◆ t0sz
gem5::ContextDescriptor::t0sz |
◆ t1sz
Bitfield<21, 16> gem5::ContextDescriptor::t1sz |
◆ tbi
Bitfield<39, 38> gem5::ContextDescriptor::tbi |
◆ tg0
Bitfield<7, 6> gem5::ContextDescriptor::tg0 |
◆ tg1
Bitfield<23, 22> gem5::ContextDescriptor::tg1 |
◆ ttb0
Bitfield<51, 4> gem5::ContextDescriptor::ttb0 |
◆ ttb1
Bitfield<51, 4> gem5::ContextDescriptor::ttb1 |
◆ uwxn
Bitfield<37> gem5::ContextDescriptor::uwxn |
◆ valid
Bitfield<31> gem5::ContextDescriptor::valid |
◆ wxn
Bitfield<36> gem5::ContextDescriptor::wxn |
The documentation for this struct was generated from the following file: