gem5  v21.1.0.2
smmu_v3_defs.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_DEFS_HH__
39 #define __DEV_ARM_SMMU_V3_DEFS_HH__
40 
41 #include <stdint.h>
42 
43 #include "base/bitunion.hh"
44 
45 namespace gem5
46 {
47 
48 enum
49 {
50  SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
51  SMMU_PAGE_ZERO_SZ = 0x10000,
52  SMMU_PAGE_ONE_SZ = 0x10000,
54 };
55 
56 enum
57 {
63 };
64 
65 enum
66 {
70 };
71 
72 enum
73 {
78 };
79 
80 enum
81 {
86 };
87 
88 enum
89 {
90  ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
91  ST_CFG_SIZE_MASK = 0x000000000000003fULL,
92  ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL,
93  ST_CFG_FMT_MASK = 0x0000000000030000ULL,
94  ST_CFG_FMT_LINEAR = 0x0000000000000000ULL,
95  ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL,
96  ST_L2_SPAN_MASK = 0x000000000000001fULL,
97  ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
98 
99  VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
100  VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
101 
102  Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
103  Q_BASE_SIZE_MASK = 0x000000000000001fULL,
104 
105  E_BASE_ENABLE_MASK = 0x8000000000000000ULL,
106  E_BASE_ADDR_MASK = 0x0000fffffffffffcULL,
107 };
108 
109 union SMMURegs
110 {
111  uint8_t data[SMMU_REG_SIZE];
112 
113  struct
114  {
115  uint32_t idr0; // 0x0000
116  uint32_t idr1; // 0x0004
117  uint32_t idr2; // 0x0008
118  uint32_t idr3; // 0x000c
119  uint32_t idr4; // 0x0010
120  uint32_t idr5; // 0x0014
121  uint32_t iidr; // 0x0018
122  uint32_t aidr; // 0x001c
123  uint32_t cr0; // 0x0020
124  uint32_t cr0ack; // 0x0024
125  uint32_t cr1; // 0x0028
126  uint32_t cr2; // 0x002c
127  uint32_t _pad1; // 0x0030
128  uint32_t _pad2; // 0x0034
129  uint32_t _pad3; // 0x0038
130  uint32_t _pad4; // 0x003c
131  uint32_t statusr; // 0x0040
132  uint32_t gbpa; // 0x0044
133  uint32_t agbpa; // 0x0048
134  uint32_t _pad5; // 0x004c
135  uint32_t irq_ctrl; // 0x0050
136  uint32_t irq_ctrlack; // 0x0054
137  uint32_t _pad6; // 0x0058
138  uint32_t _pad7; // 0x005c
139 
140  uint32_t gerror; // 0x0060
141  uint32_t gerrorn; // 0x0064
142  uint64_t gerror_irq_cfg0; // 0x0068, 64 bit
143  uint32_t gerror_irq_cfg1; // 0x0070
144  uint32_t gerror_irq_cfg2; // 0x0074
145  uint32_t _pad_1; // 0x0078
146  uint32_t _pad_2; // 0x007c
147 
148  uint64_t strtab_base; // 0x0080, 64 bit
149  uint32_t strtab_base_cfg; // 0x0088
150 
151  uint64_t cmdq_base; // 0x0090, 64 bit
152  uint32_t cmdq_prod; // 0x0098
153  uint32_t cmdq_cons; // 0x009c
154  uint64_t eventq_base; // 0x00a0, 64 bit
155  uint32_t _pad8; // 0x00a8
156  uint32_t _pad9; // 0x00ac
157  uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit
158  uint32_t eventq_irq_cfg1; // 0x00b8
159  uint32_t eventq_irq_cfg2; // 0x00bc
160  uint64_t priq_base; // 0x00c0, 64 bit
161  uint32_t _pad10; // 0x00c8
162  uint32_t _pad11; // 0x00cc
163 
164  uint64_t priq_irq_cfg0; // 0x00d0
165  uint32_t priq_irq_cfg1; // 0x00d8
166  uint32_t priq_irq_cfg2; // 0x00dc
167 
168  uint32_t _pad12[8]; // 0x00e0 - 0x0100
169  uint32_t gatos_ctrl; // 0x0100
170  uint32_t _pad13; // 0x0104
171  uint64_t gatos_sid; // 0x0108
172  uint64_t gatos_addr; // 0x0110
173  uint64_t gatos_par; // 0x0118
174  uint32_t _pad14[24]; // 0x0120
175  uint32_t vatos_sel; // 0x0180
176 
177  uint32_t _pad15[8095]; // 0x184 - 0x7ffc
178 
179  uint8_t _secure_regs[SMMU_SECURE_SZ]; // 0x8000 - 0x8180
180 
181  uint32_t _pad16[8095]; // 0x8184 - 0x10000
182 
183  // Page 1
184  uint32_t _pad17[42]; // 0x10000
185  uint32_t eventq_prod; // 0x100A8
186  uint32_t eventq_cons; // 0x100AC
187 
188  uint32_t _pad18[6]; // 0x100B0
189  uint32_t priq_prod; // 0x100C8
190  uint32_t priq_cons; // 0x100CC
191  };
192 };
193 
195 {
196  BitUnion64(DWORD0)
197  Bitfield<0> valid;
198  Bitfield<3, 1> config;
199  Bitfield<5, 4> s1fmt;
200  Bitfield<51, 6> s1ctxptr;
201  Bitfield<63, 59> s1cdmax;
202  EndBitUnion(DWORD0)
203  DWORD0 dw0;
204 
205  BitUnion64(DWORD1)
206  Bitfield<1, 0> s1dss;
207  Bitfield<3, 2> s1cir;
208  Bitfield<5, 4> s1cor;
209  Bitfield<7, 6> s1csh;
210  Bitfield<8> s2hwu59;
211  Bitfield<9> s2hwu60;
212  Bitfield<10> s2hwu61;
213  Bitfield<11> s2hwu62;
214  Bitfield<12> dre;
215  Bitfield<16, 13> cont;
216  Bitfield<17> dcp;
217  Bitfield<18> ppar;
218  Bitfield<19> mev;
219  Bitfield<27> s1stalld;
220  Bitfield<29, 28> eats;
221  Bitfield<31, 30> strw;
222  Bitfield<35, 32> memattr;
223  Bitfield<36> mtcfg;
224  Bitfield<40, 37> alloccfg;
225  Bitfield<45, 44> shcfg;
226  Bitfield<47, 46> nscfg;
227  Bitfield<49, 48> privcfg;
228  Bitfield<51, 50> instcfg;
229  EndBitUnion(DWORD1)
230  DWORD1 dw1;
231 
232  BitUnion64(DWORD2)
233  Bitfield<15, 0> s2vmid;
234  Bitfield<37, 32> s2t0sz;
235  Bitfield<39, 38> s2sl0;
236  Bitfield<41, 40> s2ir0;
237  Bitfield<43, 42> s2or0;
238  Bitfield<45, 44> s2sh0;
239  Bitfield<47, 46> s2tg;
240  Bitfield<50, 48> s2ps;
241  Bitfield<51> s2aa64;
242  Bitfield<52> s2endi;
243  Bitfield<53> s2affd;
244  Bitfield<54> s2ptw;
245  Bitfield<55> s2hd;
246  Bitfield<56> s2ha;
247  Bitfield<57> s2s;
248  Bitfield<58> s2r;
249  EndBitUnion(DWORD2)
250  DWORD2 dw2;
251 
252  BitUnion64(DWORD3)
253  Bitfield<51, 4> s2ttb;
254  EndBitUnion(DWORD3)
255  DWORD3 dw3;
256 
257  uint64_t _pad[4];
258 };
259 
261 {
262  BitUnion64(DWORD0)
263  Bitfield<5, 0> t0sz;
264  Bitfield<7, 6> tg0;
265  Bitfield<9, 8> ir0;
266  Bitfield<11, 10> or0;
267  Bitfield<13, 12> sh0;
268  Bitfield<14> epd0;
269  Bitfield<15> endi;
270  Bitfield<21, 16> t1sz;
271  Bitfield<23, 22> tg1;
272  Bitfield<25, 24> ir1;
273  Bitfield<27, 26> or1;
274  Bitfield<29, 28> sh1;
275  Bitfield<30> epd1;
276  Bitfield<31> valid;
277  Bitfield<34, 32> ips;
278  Bitfield<35> affd;
279  Bitfield<36> wxn;
280  Bitfield<37> uwxn;
281  Bitfield<39, 38> tbi;
282  Bitfield<40> pan;
283  Bitfield<41> aa64;
284  Bitfield<42> hd;
285  Bitfield<43> ha;
286  Bitfield<44> s;
287  Bitfield<45> r;
288  Bitfield<46> a;
289  Bitfield<47> aset;
290  Bitfield<63, 48> asid;
291  EndBitUnion(DWORD0)
292  DWORD0 dw0;
293 
294  BitUnion64(DWORD1)
295  Bitfield<0> nscfg0;
296  Bitfield<1> had0;
297  Bitfield<51, 4> ttb0;
298  Bitfield<60> hwu0g59;
299  Bitfield<61> hwu0g60;
300  Bitfield<62> hwu0g61;
301  Bitfield<63> hwu0g62;
302  EndBitUnion(DWORD1)
303  DWORD1 dw1;
304 
305  BitUnion64(DWORD2)
306  Bitfield<0> nscfg1;
307  Bitfield<1> had1;
308  Bitfield<51, 4> ttb1;
309  Bitfield<60> hwu1g59;
310  Bitfield<61> hwu1g60;
311  Bitfield<62> hwu1g61;
312  Bitfield<63> hwu1g62;
313  EndBitUnion(DWORD2)
314  DWORD2 dw2;
315 
316  uint64_t mair;
317  uint64_t amair;
318  uint64_t _pad[3];
319 };
320 
321 enum
322 {
328  CR0_VMW_MASK = 0x1C0,
329 };
330 
332 {
334  CMD_PRF_ADDR = 0x02,
335  CMD_CFGI_STE = 0x03,
337  CMD_CFGI_CD = 0x05,
352  CMD_ATC_INV = 0x40,
353  CMD_PRI_RESP = 0x41,
354  CMD_RESUME = 0x44,
356  CMD_SYNC = 0x46,
357 };
358 
360 {
361  BitUnion64(DWORD0)
362  Bitfield<7, 0> type;
363  Bitfield<10> ssec;
364  Bitfield<11> ssv;
365  Bitfield<31, 12> ssid;
366  Bitfield<47, 32> vmid;
367  Bitfield<63, 48> asid;
368  Bitfield<63, 32> sid;
369  EndBitUnion(DWORD0)
370  DWORD0 dw0;
371 
372  BitUnion64(DWORD1)
373  Bitfield<0> leaf;
374  Bitfield<4, 0> size;
375  Bitfield<4, 0> range;
376  Bitfield<63, 12> address;
377  EndBitUnion(DWORD1)
378  DWORD1 dw1;
379 
380  uint64_t addr() const
381  {
382  uint64_t address = (uint64_t)(dw1.address) << 12;
383  return address;
384  }
385 };
386 
388 {
389  EVT_FAULT = 0x0001,
390 };
391 
393 {
394  EVF_WRITE = 0x0001,
395 };
396 
397 struct SMMUEvent
398 {
399  uint16_t type;
400  uint16_t stag;
401  uint32_t flags;
402  uint32_t streamId;
403  uint32_t substreamId;
404  uint64_t va;
405  uint64_t ipa;
406 };
407 
408 enum
409 {
411 };
412 
413 } // namespace gem5
414 
415 #endif /* __DEV_ARM_SMMU_V3_DEFS_HH__ */
gem5::CMD_CFGI_CD
@ CMD_CFGI_CD
Definition: smmu_v3_defs.hh:337
gem5::CMD_RESUME
@ CMD_RESUME
Definition: smmu_v3_defs.hh:354
gem5::SMMURegs::_pad13
uint32_t _pad13
Definition: smmu_v3_defs.hh:170
gem5::StreamTableEntry::s2tg
Bitfield< 47, 46 > s2tg
Definition: smmu_v3_defs.hh:239
gem5::ArmISA::t0sz
Bitfield< 2, 0 > t0sz
Definition: misc_types.hh:492
gem5::STE_CONFIG_STAGE2_ONLY
@ STE_CONFIG_STAGE2_ONLY
Definition: smmu_v3_defs.hh:61
gem5::StreamTableEntry::s1ctxptr
Bitfield< 51, 6 > s1ctxptr
Definition: smmu_v3_defs.hh:200
gem5::SMMURegs::statusr
uint32_t statusr
Definition: smmu_v3_defs.hh:131
gem5::StreamTableEntry::s2hwu60
Bitfield< 9 > s2hwu60
Definition: smmu_v3_defs.hh:211
gem5::ArmISA::ips
Bitfield< 34, 32 > ips
Definition: misc_types.hh:506
gem5::STE_CONFIG_BYPASS
@ STE_CONFIG_BYPASS
Definition: smmu_v3_defs.hh:59
gem5::StreamTableEntry::eats
Bitfield< 29, 28 > eats
Definition: smmu_v3_defs.hh:220
gem5::StreamTableEntry::s2sl0
Bitfield< 39, 38 > s2sl0
Definition: smmu_v3_defs.hh:235
gem5::SMMUEventFlags
SMMUEventFlags
Definition: smmu_v3_defs.hh:392
gem5::StreamTableEntry::alloccfg
Bitfield< 40, 37 > alloccfg
Definition: smmu_v3_defs.hh:224
gem5::StreamTableEntry::s2hwu62
Bitfield< 11 > s2hwu62
Definition: smmu_v3_defs.hh:213
gem5::SMMURegs::_pad8
uint32_t _pad8
Definition: smmu_v3_defs.hh:155
gem5::CMD_CFGI_STE
@ CMD_CFGI_STE
Definition: smmu_v3_defs.hh:335
gem5::SMMUCommandType
SMMUCommandType
Definition: smmu_v3_defs.hh:331
gem5::SMMURegs::_pad7
uint32_t _pad7
Definition: smmu_v3_defs.hh:138
gem5::StreamTableEntry::s1dss
s1dss
Definition: smmu_v3_defs.hh:206
gem5::SMMU_REG_SIZE
@ SMMU_REG_SIZE
Definition: smmu_v3_defs.hh:53
gem5::StreamTableEntry
Definition: smmu_v3_defs.hh:194
gem5::SMMURegs
Definition: smmu_v3_defs.hh:109
gem5::SMMUEvent::va
uint64_t va
Definition: smmu_v3_defs.hh:404
gem5::SMMURegs::eventq_base
uint64_t eventq_base
Definition: smmu_v3_defs.hh:154
gem5::SMMUEvent::substreamId
uint32_t substreamId
Definition: smmu_v3_defs.hh:403
gem5::SMMURegs::_pad3
uint32_t _pad3
Definition: smmu_v3_defs.hh:129
gem5::CMD_CFGI_STE_RANGE
@ CMD_CFGI_STE_RANGE
Definition: smmu_v3_defs.hh:336
gem5::SMMURegs::idr2
uint32_t idr2
Definition: smmu_v3_defs.hh:117
gem5::StreamTableEntry::s2s
Bitfield< 57 > s2s
Definition: smmu_v3_defs.hh:247
gem5::CMD_TLBI_NSNH_ALL
@ CMD_TLBI_NSNH_ALL
Definition: smmu_v3_defs.hh:351
gem5::ArmISA::tbi
Bitfield< 20 > tbi
Definition: misc_types.hh:514
gem5::VMT_BASE_SIZE_MASK
@ VMT_BASE_SIZE_MASK
Definition: smmu_v3_defs.hh:100
gem5::TRANS_GRANULE_INVALID
@ TRANS_GRANULE_INVALID
Definition: smmu_v3_defs.hh:85
gem5::StreamTableEntry::memattr
Bitfield< 35, 32 > memattr
Definition: smmu_v3_defs.hh:222
gem5::CMD_PRF_ADDR
@ CMD_PRF_ADDR
Definition: smmu_v3_defs.hh:334
gem5::SMMUEventTypes
SMMUEventTypes
Definition: smmu_v3_defs.hh:387
gem5::ArmISA::asid
asid
Definition: misc_types.hh:617
gem5::CMD_TLBI_EL2_VA
@ CMD_TLBI_EL2_VA
Definition: smmu_v3_defs.hh:347
gem5::CR0_EVENTQEN_MASK
@ CR0_EVENTQEN_MASK
Definition: smmu_v3_defs.hh:325
gem5::StreamTableEntry::s1cir
Bitfield< 3, 2 > s1cir
Definition: smmu_v3_defs.hh:207
gem5::SMMUEvent::stag
uint16_t stag
Definition: smmu_v3_defs.hh:400
gem5::SMMURegs::agbpa
uint32_t agbpa
Definition: smmu_v3_defs.hh:133
gem5::SMMURegs::gatos_addr
uint64_t gatos_addr
Definition: smmu_v3_defs.hh:172
gem5::SMMURegs::eventq_prod
uint32_t eventq_prod
Definition: smmu_v3_defs.hh:185
gem5::TRANS_GRANULE_64K
@ TRANS_GRANULE_64K
Definition: smmu_v3_defs.hh:83
gem5::SMMURegs::cmdq_cons
uint32_t cmdq_cons
Definition: smmu_v3_defs.hh:153
gem5::SMMURegs::eventq_irq_cfg0
uint64_t eventq_irq_cfg0
Definition: smmu_v3_defs.hh:157
gem5::StreamTableEntry::ppar
Bitfield< 18 > ppar
Definition: smmu_v3_defs.hh:217
gem5::ST_CFG_SIZE_MASK
@ ST_CFG_SIZE_MASK
Definition: smmu_v3_defs.hh:91
gem5::CMD_TLBI_NH_VAA
@ CMD_TLBI_NH_VAA
Definition: smmu_v3_defs.hh:341
gem5::CMD_SYNC
@ CMD_SYNC
Definition: smmu_v3_defs.hh:356
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::TRANS_GRANULE_16K
@ TRANS_GRANULE_16K
Definition: smmu_v3_defs.hh:84
gem5::SMMU_PAGE_ZERO_SZ
@ SMMU_PAGE_ZERO_SZ
Definition: smmu_v3_defs.hh:51
gem5::SMMURegs::gbpa
uint32_t gbpa
Definition: smmu_v3_defs.hh:132
gem5::CMD_TLBI_S2_IPA
@ CMD_TLBI_S2_IPA
Definition: smmu_v3_defs.hh:349
gem5::ArmISA::tg0
Bitfield< 14 > tg0
Definition: misc_types.hh:498
gem5::SMMURegs::strtab_base_cfg
uint32_t strtab_base_cfg
Definition: smmu_v3_defs.hh:149
gem5::StreamTableEntry::s2affd
Bitfield< 53 > s2affd
Definition: smmu_v3_defs.hh:243
gem5::StreamTableEntry::s2vmid
s2vmid
Definition: smmu_v3_defs.hh:233
gem5::ArmISA::ir1
Bitfield< 3, 2 > ir1
Definition: misc_types.hh:599
gem5::CMD_ATC_INV
@ CMD_ATC_INV
Definition: smmu_v3_defs.hh:352
gem5::SMMURegs::irq_ctrl
uint32_t irq_ctrl
Definition: smmu_v3_defs.hh:135
gem5::CR0_SMMUEN_MASK
@ CR0_SMMUEN_MASK
Definition: smmu_v3_defs.hh:323
gem5::SMMURegs::irq_ctrlack
uint32_t irq_ctrlack
Definition: smmu_v3_defs.hh:136
gem5::StreamTableEntry::s1fmt
Bitfield< 5, 4 > s1fmt
Definition: smmu_v3_defs.hh:199
gem5::SMMURegs::cr0ack
uint32_t cr0ack
Definition: smmu_v3_defs.hh:124
gem5::ArmISA::t1sz
Bitfield< 18, 16 > t1sz
Definition: misc_types.hh:499
gem5::STAGE1_CFG_1L
@ STAGE1_CFG_1L
Definition: smmu_v3_defs.hh:67
gem5::SMMURegs::cmdq_prod
uint32_t cmdq_prod
Definition: smmu_v3_defs.hh:152
gem5::StreamTableEntry::s1csh
Bitfield< 7, 6 > s1csh
Definition: smmu_v3_defs.hh:209
gem5::VMT_BASE_ADDR_MASK
@ VMT_BASE_ADDR_MASK
Definition: smmu_v3_defs.hh:99
gem5::ContextDescriptor
Definition: smmu_v3_defs.hh:260
gem5::ST_L2_ADDR_MASK
@ ST_L2_ADDR_MASK
Definition: smmu_v3_defs.hh:97
gem5::CR0_ATSCHK_MASK
@ CR0_ATSCHK_MASK
Definition: smmu_v3_defs.hh:327
gem5::SMMURegs::gerror_irq_cfg2
uint32_t gerror_irq_cfg2
Definition: smmu_v3_defs.hh:144
gem5::StreamTableEntry::privcfg
Bitfield< 49, 48 > privcfg
Definition: smmu_v3_defs.hh:227
gem5::StreamTableEntry::nscfg
Bitfield< 47, 46 > nscfg
Definition: smmu_v3_defs.hh:226
gem5::StreamTableEntry::s2endi
Bitfield< 52 > s2endi
Definition: smmu_v3_defs.hh:242
gem5::SMMURegs::_pad_2
uint32_t _pad_2
Definition: smmu_v3_defs.hh:146
gem5::StreamTableEntry::mev
Bitfield< 19 > mev
Definition: smmu_v3_defs.hh:218
gem5::SMMURegs::gerrorn
uint32_t gerrorn
Definition: smmu_v3_defs.hh:141
gem5::SMMURegs::priq_prod
uint32_t priq_prod
Definition: smmu_v3_defs.hh:189
gem5::ArmISA::epd1
Bitfield< 23 > epd1
Definition: misc_types.hh:501
gem5::SMMURegs::idr1
uint32_t idr1
Definition: smmu_v3_defs.hh:116
gem5::SMMURegs::idr4
uint32_t idr4
Definition: smmu_v3_defs.hh:119
gem5::SMMURegs::idr3
uint32_t idr3
Definition: smmu_v3_defs.hh:118
gem5::Q_BASE_ADDR_MASK
@ Q_BASE_ADDR_MASK
Definition: smmu_v3_defs.hh:102
gem5::SMMURegs::vatos_sel
uint32_t vatos_sel
Definition: smmu_v3_defs.hh:175
gem5::SMMUEvent::flags
uint32_t flags
Definition: smmu_v3_defs.hh:401
gem5::SMMURegs::_secure_regs
uint8_t _secure_regs[SMMU_SECURE_SZ]
Definition: smmu_v3_defs.hh:179
gem5::CMD_TLBI_EL3_ALL
@ CMD_TLBI_EL3_ALL
Definition: smmu_v3_defs.hh:343
gem5::StreamTableEntry::instcfg
Bitfield< 51, 50 > instcfg
Definition: smmu_v3_defs.hh:228
gem5::StreamTableEntry::s2ps
Bitfield< 50, 48 > s2ps
Definition: smmu_v3_defs.hh:240
gem5::StreamTableEntry::dre
Bitfield< 12 > dre
Definition: smmu_v3_defs.hh:214
gem5::StreamTableEntry::s2aa64
Bitfield< 51 > s2aa64
Definition: smmu_v3_defs.hh:241
gem5::SMMURegs::_pad9
uint32_t _pad9
Definition: smmu_v3_defs.hh:156
gem5::ArmISA::epd0
Bitfield< 7 > epd0
Definition: misc_types.hh:494
gem5::StreamTableEntry::strw
Bitfield< 31, 30 > strw
Definition: smmu_v3_defs.hh:221
gem5::StreamTableEntry::s2sh0
Bitfield< 45, 44 > s2sh0
Definition: smmu_v3_defs.hh:238
gem5::StreamTableEntry::config
Bitfield< 3, 1 > config
Definition: smmu_v3_defs.hh:198
gem5::SMMURegs::_pad1
uint32_t _pad1
Definition: smmu_v3_defs.hh:127
gem5::SMMURegs::idr5
uint32_t idr5
Definition: smmu_v3_defs.hh:120
gem5::ST_CFG_SPLIT_SHIFT
@ ST_CFG_SPLIT_SHIFT
Definition: smmu_v3_defs.hh:74
gem5::CMD_TLBI_EL2_VAA
@ CMD_TLBI_EL2_VAA
Definition: smmu_v3_defs.hh:348
gem5::ArmISA::wxn
Bitfield< 19 > wxn
Definition: misc_types.hh:359
gem5::StreamTableEntry::_pad
uint64_t _pad[4]
Definition: smmu_v3_defs.hh:257
bitunion.hh
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::STAGE1_CFG_2L_64K
@ STAGE1_CFG_2L_64K
Definition: smmu_v3_defs.hh:69
gem5::StreamTableEntry::s2ptw
Bitfield< 54 > s2ptw
Definition: smmu_v3_defs.hh:244
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::SMMURegs::_pad4
uint32_t _pad4
Definition: smmu_v3_defs.hh:130
gem5::SMMURegs::priq_base
uint64_t priq_base
Definition: smmu_v3_defs.hh:160
gem5::ArmISA::ir0
ir0
Definition: misc_types.hh:598
gem5::SMMU_MAX_TRANS_ID
@ SMMU_MAX_TRANS_ID
Definition: smmu_v3_defs.hh:410
gem5::SMMURegs::_pad12
uint32_t _pad12[8]
Definition: smmu_v3_defs.hh:168
gem5::ST_CFG_FMT_MASK
@ ST_CFG_FMT_MASK
Definition: smmu_v3_defs.hh:93
gem5::ArmISA::pan
Bitfield< 22 > pan
Definition: misc_types.hh:58
gem5::ST_CFG_FMT_2LEVEL
@ ST_CFG_FMT_2LEVEL
Definition: smmu_v3_defs.hh:95
gem5::ArmISA::or1
Bitfield< 19, 18 > or1
Definition: misc_types.hh:607
gem5::SMMURegs::eventq_irq_cfg1
uint32_t eventq_irq_cfg1
Definition: smmu_v3_defs.hh:158
gem5::SMMURegs::gerror
uint32_t gerror
Definition: smmu_v3_defs.hh:140
gem5::STE_CONFIG_STAGE1_AND_2
@ STE_CONFIG_STAGE1_AND_2
Definition: smmu_v3_defs.hh:62
gem5::StreamTableEntry::s2hwu61
Bitfield< 10 > s2hwu61
Definition: smmu_v3_defs.hh:212
gem5::SMMUEvent::ipa
uint64_t ipa
Definition: smmu_v3_defs.hh:405
gem5::ST_BASE_ADDR_MASK
@ ST_BASE_ADDR_MASK
Definition: smmu_v3_defs.hh:90
gem5::SMMURegs::gatos_ctrl
uint32_t gatos_ctrl
Definition: smmu_v3_defs.hh:169
gem5::StreamTableEntry::s2r
Bitfield< 58 > s2r
Definition: smmu_v3_defs.hh:248
gem5::StreamTableEntry::s1cdmax
Bitfield< 63, 59 > s1cdmax
Definition: smmu_v3_defs.hh:201
gem5::STAGE1_CFG_2L_4K
@ STAGE1_CFG_2L_4K
Definition: smmu_v3_defs.hh:68
gem5::SMMURegs::_pad15
uint32_t _pad15[8095]
Definition: smmu_v3_defs.hh:177
gem5::ST_CD_ADDR_SHIFT
@ ST_CD_ADDR_SHIFT
Definition: smmu_v3_defs.hh:75
gem5::SMMURegs::gatos_par
uint64_t gatos_par
Definition: smmu_v3_defs.hh:173
gem5::SMMURegs::gerror_irq_cfg0
uint64_t gerror_irq_cfg0
Definition: smmu_v3_defs.hh:142
gem5::CMD_TLBI_EL3_VA
@ CMD_TLBI_EL3_VA
Definition: smmu_v3_defs.hh:344
gem5::SMMUEvent::type
uint16_t type
Definition: smmu_v3_defs.hh:399
gem5::SMMURegs::idr0
uint32_t idr0
Definition: smmu_v3_defs.hh:115
gem5::StreamTableEntry::BitUnion64
BitUnion64(DWORD0) Bitfield< 0 > valid
gem5::SMMURegs::iidr
uint32_t iidr
Definition: smmu_v3_defs.hh:121
gem5::SMMURegs::eventq_cons
uint32_t eventq_cons
Definition: smmu_v3_defs.hh:186
gem5::SMMURegs::eventq_irq_cfg2
uint32_t eventq_irq_cfg2
Definition: smmu_v3_defs.hh:159
gem5::ArmISA::or0
Bitfield< 17, 16 > or0
Definition: misc_types.hh:606
gem5::TRANS_GRANULE_4K
@ TRANS_GRANULE_4K
Definition: smmu_v3_defs.hh:82
gem5::ST_CFG_SPLIT_MASK
@ ST_CFG_SPLIT_MASK
Definition: smmu_v3_defs.hh:92
gem5::StreamTableEntry::s2or0
Bitfield< 43, 42 > s2or0
Definition: smmu_v3_defs.hh:237
gem5::SMMURegs::_pad14
uint32_t _pad14[24]
Definition: smmu_v3_defs.hh:174
gem5::SMMURegs::data
uint8_t data[SMMU_REG_SIZE]
Definition: smmu_v3_defs.hh:111
gem5::StreamTableEntry::s2hd
Bitfield< 55 > s2hd
Definition: smmu_v3_defs.hh:245
gem5::StreamTableEntry::s2ir0
Bitfield< 41, 40 > s2ir0
Definition: smmu_v3_defs.hh:236
gem5::SMMURegs::_pad18
uint32_t _pad18[6]
Definition: smmu_v3_defs.hh:188
gem5::SMMURegs::_pad6
uint32_t _pad6
Definition: smmu_v3_defs.hh:137
gem5::SMMURegs::priq_irq_cfg1
uint32_t priq_irq_cfg1
Definition: smmu_v3_defs.hh:165
gem5::StreamTableEntry::mtcfg
Bitfield< 36 > mtcfg
Definition: smmu_v3_defs.hh:223
gem5::STE_CONFIG_STAGE1_ONLY
@ STE_CONFIG_STAGE1_ONLY
Definition: smmu_v3_defs.hh:60
gem5::SMMUEvent
Definition: smmu_v3_defs.hh:397
gem5::SMMUEvent::streamId
uint32_t streamId
Definition: smmu_v3_defs.hh:402
gem5::SMMURegs::cr2
uint32_t cr2
Definition: smmu_v3_defs.hh:126
gem5::ST_L2_SPAN_MASK
@ ST_L2_SPAN_MASK
Definition: smmu_v3_defs.hh:96
gem5::SMMURegs::_pad16
uint32_t _pad16[8095]
Definition: smmu_v3_defs.hh:181
gem5::CMD_TLBI_NH_ASID
@ CMD_TLBI_NH_ASID
Definition: smmu_v3_defs.hh:340
gem5::EVF_WRITE
@ EVF_WRITE
Definition: smmu_v3_defs.hh:394
gem5::SMMURegs::priq_irq_cfg2
uint32_t priq_irq_cfg2
Definition: smmu_v3_defs.hh:166
gem5::CMD_TLBI_EL2_ALL
@ CMD_TLBI_EL2_ALL
Definition: smmu_v3_defs.hh:345
gem5::SMMURegs::_pad_1
uint32_t _pad_1
Definition: smmu_v3_defs.hh:145
gem5::SMMURegs::_pad10
uint32_t _pad10
Definition: smmu_v3_defs.hh:161
gem5::ArmISA::uwxn
Bitfield< 20 > uwxn
Definition: misc_types.hh:355
gem5::CMD_TLBI_NH_VA
@ CMD_TLBI_NH_VA
Definition: smmu_v3_defs.hh:342
gem5::StreamTableEntry::cont
Bitfield< 16, 13 > cont
Definition: smmu_v3_defs.hh:215
gem5::SMMURegs::_pad2
uint32_t _pad2
Definition: smmu_v3_defs.hh:128
gem5::ST_CFG_FMT_LINEAR
@ ST_CFG_FMT_LINEAR
Definition: smmu_v3_defs.hh:94
gem5::CMD_STALL_TERM
@ CMD_STALL_TERM
Definition: smmu_v3_defs.hh:355
gem5::SMMURegs::gatos_sid
uint64_t gatos_sid
Definition: smmu_v3_defs.hh:171
gem5::ArmISA::tg1
Bitfield< 30 > tg1
Definition: misc_types.hh:505
gem5::StreamTableEntry::EndBitUnion
EndBitUnion(DWORD0) DWORD0 dw0
gem5::SMMURegs::strtab_base
uint64_t strtab_base
Definition: smmu_v3_defs.hh:148
gem5::SMMURegs::priq_cons
uint32_t priq_cons
Definition: smmu_v3_defs.hh:190
gem5::SMMUCommand
Definition: smmu_v3_defs.hh:359
gem5::CMD_PRI_RESP
@ CMD_PRI_RESP
Definition: smmu_v3_defs.hh:353
gem5::StreamTableEntry::s1cor
Bitfield< 5, 4 > s1cor
Definition: smmu_v3_defs.hh:208
gem5::SMMURegs::cr0
uint32_t cr0
Definition: smmu_v3_defs.hh:123
gem5::SMMURegs::_pad5
uint32_t _pad5
Definition: smmu_v3_defs.hh:134
gem5::CMD_TLBI_S12_VMALL
@ CMD_TLBI_S12_VMALL
Definition: smmu_v3_defs.hh:350
gem5::E_BASE_ENABLE_MASK
@ E_BASE_ENABLE_MASK
Definition: smmu_v3_defs.hh:105
gem5::SMMURegs::cmdq_base
uint64_t cmdq_base
Definition: smmu_v3_defs.hh:151
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::SMMURegs::_pad17
uint32_t _pad17[42]
Definition: smmu_v3_defs.hh:184
gem5::CR0_CMDQEN_MASK
@ CR0_CMDQEN_MASK
Definition: smmu_v3_defs.hh:326
gem5::CR0_PRIQEN_MASK
@ CR0_PRIQEN_MASK
Definition: smmu_v3_defs.hh:324
gem5::CMD_TLBI_EL2_ASID
@ CMD_TLBI_EL2_ASID
Definition: smmu_v3_defs.hh:346
gem5::StreamTableEntry::s2hwu59
Bitfield< 8 > s2hwu59
Definition: smmu_v3_defs.hh:210
gem5::STE_CONFIG_ABORT
@ STE_CONFIG_ABORT
Definition: smmu_v3_defs.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SMMU_PAGE_ONE_SZ
@ SMMU_PAGE_ONE_SZ
Definition: smmu_v3_defs.hh:52
gem5::CMD_CFGI_CD_ALL
@ CMD_CFGI_CD_ALL
Definition: smmu_v3_defs.hh:338
gem5::SMMURegs::aidr
uint32_t aidr
Definition: smmu_v3_defs.hh:122
gem5::ArmISA::ha
Bitfield< 39 > ha
Definition: misc_types.hh:543
gem5::CD_TTB_SHIFT
@ CD_TTB_SHIFT
Definition: smmu_v3_defs.hh:76
gem5::SMMURegs::priq_irq_cfg0
uint64_t priq_irq_cfg0
Definition: smmu_v3_defs.hh:164
gem5::ArmISA::sh1
SignedBitfield< 31, 16 > sh1
Definition: int.hh:59
gem5::CR0_VMW_MASK
@ CR0_VMW_MASK
Definition: smmu_v3_defs.hh:328
gem5::ArmISA::hd
Bitfield< 40 > hd
Definition: misc_types.hh:544
gem5::CMD_TLBI_NH_ALL
@ CMD_TLBI_NH_ALL
Definition: smmu_v3_defs.hh:339
gem5::StreamTableEntry::s2ttb
s2ttb
Definition: smmu_v3_defs.hh:253
gem5::StreamTableEntry::s1stalld
Bitfield< 27 > s1stalld
Definition: smmu_v3_defs.hh:219
gem5::StreamTableEntry::s2ha
Bitfield< 56 > s2ha
Definition: smmu_v3_defs.hh:246
gem5::StreamTableEntry::dcp
Bitfield< 17 > dcp
Definition: smmu_v3_defs.hh:216
gem5::E_BASE_ADDR_MASK
@ E_BASE_ADDR_MASK
Definition: smmu_v3_defs.hh:106
gem5::SMMU_SECURE_SZ
@ SMMU_SECURE_SZ
Definition: smmu_v3_defs.hh:50
gem5::STE_S2TTB_SHIFT
@ STE_S2TTB_SHIFT
Definition: smmu_v3_defs.hh:77
gem5::StreamTableEntry::s2t0sz
Bitfield< 37, 32 > s2t0sz
Definition: smmu_v3_defs.hh:234
gem5::SMMURegs::_pad11
uint32_t _pad11
Definition: smmu_v3_defs.hh:162
gem5::SMMURegs::gerror_irq_cfg1
uint32_t gerror_irq_cfg1
Definition: smmu_v3_defs.hh:143
gem5::StreamTableEntry::shcfg
Bitfield< 45, 44 > shcfg
Definition: smmu_v3_defs.hh:225
gem5::CMD_PRF_CONFIG
@ CMD_PRF_CONFIG
Definition: smmu_v3_defs.hh:333
gem5::SMMURegs::cr1
uint32_t cr1
Definition: smmu_v3_defs.hh:125
gem5::Q_BASE_SIZE_MASK
@ Q_BASE_SIZE_MASK
Definition: smmu_v3_defs.hh:103
gem5::EVT_FAULT
@ EVT_FAULT
Definition: smmu_v3_defs.hh:389
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::sh0
SignedBitfield< 15, 0 > sh0
Definition: int.hh:60

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