gem5  v21.1.0.2
Public Member Functions | Public Attributes | List of all members
gem5::GicV2::BankedRegs Struct Reference

Registers "banked for each connected processor" per ARM IHI0048B. More...

#include <gic_v2.hh>

Inheritance diagram for gem5::GicV2::BankedRegs:
gem5::Serializable

Public Member Functions

void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
 BankedRegs ()
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 

Public Attributes

uint32_t intEnabled
 GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt. More...
 
uint32_t pendingInt
 GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt. More...
 
uint32_t activeInt
 GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt. More...
 
uint32_t intGroup
 GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt. More...
 
uint32_t intConfig [2]
 GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt. More...
 
uint8_t intPriority [SGI_MAX+PPI_MAX]
 GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs. More...
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 

Detailed Description

Registers "banked for each connected processor" per ARM IHI0048B.

Definition at line 183 of file gic_v2.hh.

Constructor & Destructor Documentation

◆ BankedRegs()

gem5::GicV2::BankedRegs::BankedRegs ( )
inline

Definition at line 212 of file gic_v2.hh.

Member Function Documentation

◆ serialize()

void gem5::GicV2::BankedRegs::serialize ( CheckpointOut cp) const
overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 1032 of file gic_v2.cc.

References activeInt, intConfig, intEnabled, intGroup, intPriority, pendingInt, gem5::GicV2::PPI_MAX, SERIALIZE_ARRAY, SERIALIZE_SCALAR, and gem5::GicV2::SGI_MAX.

◆ unserialize()

void gem5::GicV2::BankedRegs::unserialize ( CheckpointIn cp)
overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 1092 of file gic_v2.cc.

References gem5::GicV2::activeInt, gem5::GicV2::intConfig, gem5::GicV2::intEnabled, gem5::GicV2::intGroup, gem5::GicV2::intPriority, gem5::GicV2::pendingInt, gem5::GicV2::PPI_MAX, gem5::GicV2::SGI_MAX, UNSERIALIZE_ARRAY, and UNSERIALIZE_SCALAR.

Referenced by gem5::GicV2::unserialize().

Member Data Documentation

◆ activeInt

uint32_t gem5::GicV2::BankedRegs::activeInt

GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt.

Definition at line 195 of file gic_v2.hh.

Referenced by gem5::GicV2::getActiveInt(), and serialize().

◆ intConfig

uint32_t gem5::GicV2::BankedRegs::intConfig[2]

GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt.

Definition at line 203 of file gic_v2.hh.

Referenced by gem5::GicV2::getIntConfig(), and serialize().

◆ intEnabled

uint32_t gem5::GicV2::BankedRegs::intEnabled

GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt.

Definition at line 187 of file gic_v2.hh.

Referenced by gem5::GicV2::getIntEnabled(), and serialize().

◆ intGroup

uint32_t gem5::GicV2::BankedRegs::intGroup

GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt.

Definition at line 199 of file gic_v2.hh.

Referenced by gem5::GicV2::getIntGroup(), and serialize().

◆ intPriority

uint8_t gem5::GicV2::BankedRegs::intPriority[SGI_MAX+PPI_MAX]

GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs.

Definition at line 207 of file gic_v2.hh.

Referenced by gem5::GicV2::getIntPriority(), and serialize().

◆ pendingInt

uint32_t gem5::GicV2::BankedRegs::pendingInt

GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt.

Definition at line 191 of file gic_v2.hh.

Referenced by gem5::GicV2::getPendingInt(), and serialize().


The documentation for this struct was generated from the following files:

Generated on Tue Sep 21 2021 12:27:38 for gem5 by doxygen 1.8.17