gem5  v21.1.0.2
gic_v2.hh
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40 
41 
46 #ifndef __DEV_ARM_GICV2_H__
47 #define __DEV_ARM_GICV2_H__
48 
49 #include <vector>
50 
51 #include "arch/arm/interrupts.hh"
52 #include "base/addr_range.hh"
53 #include "base/bitunion.hh"
54 #include "dev/arm/base_gic.hh"
55 #include "dev/io_device.hh"
56 #include "dev/platform.hh"
57 #include "params/GicV2.hh"
58 
59 namespace gem5
60 {
61 
62 class GicV2 : public BaseGic, public BaseGicRegisters
63 {
64  protected:
65  // distributor memory addresses
66  enum
67  {
68  GICD_CTLR = 0x000, // control register
69  GICD_TYPER = 0x004, // controller type
70  GICD_IIDR = 0x008, // implementer id
71  GICD_SGIR = 0xf00, // software generated interrupt
72  GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
73  GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
74  GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
75  GICD_PIDR3 = 0xfec, // distributor peripheral ID3
76 
77  DIST_SIZE = 0x1000,
78  };
79 
80  const uint32_t gicdPIDR;
81  const uint32_t gicdIIDR;
82  const uint32_t giccIIDR;
83 
84  static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
85  static const AddrRange GICD_ISENABLER; // interrupt set enable
86  static const AddrRange GICD_ICENABLER; // interrupt clear enable
87  static const AddrRange GICD_ISPENDR; // set pending interrupt
88  static const AddrRange GICD_ICPENDR; // clear pending interrupt
89  static const AddrRange GICD_ISACTIVER; // active bit registers
90  static const AddrRange GICD_ICACTIVER; // clear bit registers
91  static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
92  static const AddrRange GICD_ITARGETSR; // processor target registers
93  static const AddrRange GICD_ICFGR; // interrupt config registers
94 
95  // cpu memory addresses
96  enum
97  {
98  GICC_CTLR = 0x00, // CPU control register
99  GICC_PMR = 0x04, // Interrupt priority mask
100  GICC_BPR = 0x08, // binary point register
101  GICC_IAR = 0x0C, // interrupt ack register
102  GICC_EOIR = 0x10, // end of interrupt
103  GICC_RPR = 0x14, // running priority
104  GICC_HPPIR = 0x18, // highest pending interrupt
105  GICC_ABPR = 0x1c, // aliased binary point
106  GICC_APR0 = 0xd0, // active priority register 0
107  GICC_APR1 = 0xd4, // active priority register 1
108  GICC_APR2 = 0xd8, // active priority register 2
109  GICC_APR3 = 0xdc, // active priority register 3
110  GICC_IIDR = 0xfc, // cpu interface id register
111  GICC_DIR = 0x1000, // deactive interrupt register
112  };
113 
114  static const int SGI_MAX = 16; // Number of Software Gen Interrupts
115  static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
116 
118  static const int SGI_MASK = 0xFFFF0000;
119 
121  static const int NN_CONFIG_MASK = 0x55555555;
122 
123  static const int CPU_MAX = 256; // Max number of supported CPU interfaces
124  static const int SPURIOUS_INT = 1023;
125  static const int INT_BITS_MAX = 32;
126  static const int INT_LINES_MAX = 1020;
128 
131  static const int GICC_BPR_MINIMUM = 2;
132 
133  BitUnion32(SWI)
134  Bitfield<3,0> sgi_id;
135  Bitfield<23,16> cpu_list;
136  Bitfield<25,24> list_type;
137  EndBitUnion(SWI)
138 
139  BitUnion32(IAR)
140  Bitfield<9,0> ack_id;
141  Bitfield<12,10> cpu_id;
142  EndBitUnion(IAR)
143 
144  BitUnion32(CTLR)
145  Bitfield<3> fiqEn;
146  Bitfield<1> enableGrp1;
147  Bitfield<0> enableGrp0;
149 
150  protected: /* Params */
152  const AddrRange distRange;
153 
155  const AddrRange cpuRange;
156 
159 
162 
165 
168 
169  protected:
171  bool enabled;
172 
174  const bool haveGem5Extensions;
175 
178 
180  uint32_t itLines;
181 
183  struct BankedRegs : public Serializable
184  {
187  uint32_t intEnabled;
188 
191  uint32_t pendingInt;
192 
195  uint32_t activeInt;
196 
199  uint32_t intGroup;
200 
203  uint32_t intConfig[2];
204 
208 
209  void serialize(CheckpointOut &cp) const override;
210  void unserialize(CheckpointIn &cp) override;
211 
213  intEnabled(0), pendingInt(0), activeInt(0),
214  intGroup(0), intConfig {0}, intPriority {0}
215  {}
216  };
218 
220 
225 
226  uint32_t&
227  getIntEnabled(ContextID ctx, uint32_t ix)
228  {
229  if (ix == 0) {
230  return getBankedRegs(ctx).intEnabled;
231  } else {
232  return intEnabled[ix - 1];
233  }
234  }
235 
240 
241  uint32_t&
242  getPendingInt(ContextID ctx, uint32_t ix)
243  {
244  assert(ix < INT_BITS_MAX);
245  if (ix == 0) {
246  return getBankedRegs(ctx).pendingInt;
247  } else {
248  return pendingInt[ix - 1];
249  }
250  }
251 
255  uint32_t activeInt[INT_BITS_MAX-1];
256 
257  uint32_t&
258  getActiveInt(ContextID ctx, uint32_t ix)
259  {
260  assert(ix < INT_BITS_MAX);
261  if (ix == 0) {
262  return getBankedRegs(ctx).activeInt;
263  } else {
264  return activeInt[ix - 1];
265  }
266  }
267 
271  uint32_t intGroup[INT_BITS_MAX-1];
272 
273  uint32_t&
274  getIntGroup(ContextID ctx, uint32_t ix)
275  {
276  assert(ix < INT_BITS_MAX);
277  if (ix == 0) {
278  return getBankedRegs(ctx).intGroup;
279  } else {
280  return intGroup[ix - 1];
281  }
282  }
283 
285  uint32_t iccrpr[CPU_MAX];
286 
292 
293  uint8_t&
294  getIntPriority(ContextID ctx, uint32_t ix)
295  {
296  assert(ix < INT_LINES_MAX);
297  if (ix < SGI_MAX + PPI_MAX) {
298  return getBankedRegs(ctx).intPriority[ix];
299  } else {
300  return intPriority[ix - (SGI_MAX + PPI_MAX)];
301  }
302  }
303 
308  uint32_t intConfig[INT_BITS_MAX*2 - 2];
309 
316  uint32_t&
317  getIntConfig(ContextID ctx, uint32_t ix)
318  {
319  assert(ix < INT_BITS_MAX*2);
320  if (ix < 2) {
322  return getBankedRegs(ctx).intConfig[ix];
323  } else {
324  return intConfig[ix - 2];
325  }
326  }
327 
332 
333  uint8_t
334  getCpuTarget(ContextID ctx, uint32_t ix) const
335  {
336  assert(ctx < sys->threads.numRunning());
337  assert(ix < INT_LINES_MAX);
338  if (ix < SGI_MAX + PPI_MAX) {
339  // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
340  // field returns a value that corresponds only to the processor
341  // reading the register."
342  uint32_t ctx_mask;
343  if (gem5ExtensionsEnabled) {
344  ctx_mask = ctx;
345  } else {
346  fatal_if(ctx >= 8,
347  "%s requires the gem5_extensions parameter to support "
348  "more than 8 cores\n", name());
349  // convert the CPU id number into a bit mask
350  ctx_mask = 1 << ctx;
351  }
352  return ctx_mask;
353  } else {
354  return cpuTarget[ix - 32];
355  }
356  }
357 
358  bool
359  isLevelSensitive(ContextID ctx, uint32_t int_num)
360  {
361  if (int_num == SPURIOUS_INT) {
362  return false;
363  } else {
364  const auto ix = intNumToWord(int_num * 2);
365  const uint8_t cfg_hi = intNumToBit(int_num * 2) + 1;
366  return bits(getIntConfig(ctx, ix), cfg_hi) == 0;
367  }
368  }
369 
370  bool
371  isGroup0(ContextID ctx, uint32_t int_num)
372  {
373  const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
374  return !bits(group_reg, intNumToBit(int_num));
375  }
376 
387  bool
388  isFiq(ContextID ctx, uint32_t int_num)
389  {
390  const bool is_group0 = isGroup0(ctx, int_num);
391  const bool use_fiq = cpuControl[ctx].fiqEn;
392 
393  if (is_group0 && use_fiq) {
394  return true;
395  } else {
396  return false;
397  }
398  }
399 
403  bool
405  {
406  return cpuControl[ctx].enableGrp0 ||
407  cpuControl[ctx].enableGrp1;
408  }
409 
414 
417  uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
418 
420  uint8_t cpuBpr[CPU_MAX];
421 
424 
431 
437 
442 
446  void softInt(ContextID ctx, SWI swi);
447 
451  virtual void updateIntState(int hint);
452 
455  void updateRunPri();
456 
458  uint64_t genSwiMask(int cpu);
459 
460  int intNumToWord(int num) const { return num >> 5; }
461  int intNumToBit(int num) const { return num % 32; }
462 
464  void clearInt(ContextID ctx, uint32_t int_num);
465 
469  void postInt(uint32_t cpu, Tick when);
470  void postFiq(uint32_t cpu, Tick when);
471 
475  void postDelayedInt(uint32_t cpu);
476  void postDelayedFiq(uint32_t cpu);
477 
481 
482  public:
483  using Params = GicV2Params;
484  GicV2(const Params &p);
485  ~GicV2();
486 
487  DrainState drain() override;
488  void drainResume() override;
489 
490  void serialize(CheckpointOut &cp) const override;
491  void unserialize(CheckpointIn &cp) override;
492 
493  public: /* PioDevice */
494  AddrRangeList getAddrRanges() const override { return addrRanges; }
495 
499  Tick read(PacketPtr pkt) override;
500 
504  Tick write(PacketPtr pkt) override;
505 
506  public: /* BaseGic */
507  void sendInt(uint32_t number) override;
508  void clearInt(uint32_t number) override;
509 
510  void sendPPInt(uint32_t num, uint32_t cpu) override;
511  void clearPPInt(uint32_t num, uint32_t cpu) override;
512 
513  bool supportsVersion(GicVersion version) override;
514 
515  protected:
520  uint32_t readDistributor(ContextID ctx, Addr daddr,
521  size_t resp_sz);
522  uint32_t
523  readDistributor(ContextID ctx, Addr daddr) override
524  {
525  return readDistributor(ctx, daddr, 4);
526  }
527 
531  Tick readCpu(PacketPtr pkt);
532  uint32_t readCpu(ContextID ctx, Addr daddr) override;
533 
538  void writeDistributor(ContextID ctx, Addr daddr,
539  uint32_t data, size_t data_sz);
540  void
541  writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
542  {
543  return writeDistributor(ctx, daddr, data, 4);
544  }
545 
549  Tick writeCpu(PacketPtr pkt);
550  void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
551 };
552 
553 } // namespace gem5
554 
555 #endif //__DEV_ARM_GIC_H__
gem5::GicV2::clearInt
void clearInt(ContextID ctx, uint32_t int_num)
Clears a cpu IRQ or FIQ signal.
Definition: gic_v2.cc:923
gem5::GicV2::BankedRegs::BankedRegs
BankedRegs()
Definition: gic_v2.hh:212
gem5::GicV2::BankedRegs::activeInt
uint32_t activeInt
GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:195
gem5::GicV2::EndBitUnion
EndBitUnion(SWI) BitUnion32(IAR) Bitfield< 9
gem5::GicV2::iccrpr
uint32_t iccrpr[CPU_MAX]
read only running priority register, 1 per cpu
Definition: gic_v2.hh:285
io_device.hh
gem5::GicV2::SGI_MAX
static const int SGI_MAX
Definition: gic_v2.hh:114
gem5::GicV2::GICD_IPRIORITYR
static const AddrRange GICD_IPRIORITYR
Definition: gic_v2.hh:91
gem5::GicV2::intLatency
const Tick intLatency
Latency for a interrupt to get to CPU.
Definition: gic_v2.hh:167
gem5::GicV2::writeDistributor
Tick writeDistributor(PacketPtr pkt)
Handle a write to the distributor portion of the GIC.
Definition: gic_v2.cc:389
gem5::GicV2::cpuPpiPending
uint32_t cpuPpiPending[CPU_MAX]
One bit per private peripheral interrupt.
Definition: gic_v2.hh:440
gem5::GicV2::enableGrp0
Bitfield< 0 > enableGrp0
Definition: gic_v2.hh:147
gem5::GicV2::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v2.cc:1043
gem5::GicV2::GICC_APR3
@ GICC_APR3
Definition: gic_v2.hh:109
gem5::GicV2::activeInt
uint32_t activeInt[INT_BITS_MAX-1]
GICD_I{S,C}ACTIVER{1..31} interrupt active bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:255
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::GicV2::GICD_SGIR
@ GICD_SGIR
Definition: gic_v2.hh:71
gem5::GicV2::softInt
void softInt(ContextID ctx, SWI swi)
software generated interrupt
Definition: gic_v2.cc:651
gem5::GicV2::GICD_CTLR
@ GICD_CTLR
Definition: gic_v2.hh:68
gem5::GicV2::getActiveInt
uint32_t & getActiveInt(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:258
gem5::GicV2::getIntGroup
uint32_t & getIntGroup(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:274
gem5::GicV2::pendingInt
uint32_t pendingInt[INT_BITS_MAX-1]
GICD_I{S,C}PENDR{1..31} interrupt pending bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:239
gem5::GicV2::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: gic_v2.cc:991
gem5::GicV2::cpuPpiActive
uint32_t cpuPpiActive[CPU_MAX]
Definition: gic_v2.hh:441
gem5::GicV2::INT_LINES_MAX
static const int INT_LINES_MAX
Definition: gic_v2.hh:126
gem5::GicV2::GICC_RPR
@ GICC_RPR
Definition: gic_v2.hh:103
gem5::GicV2::GICC_EOIR
@ GICC_EOIR
Definition: gic_v2.hh:102
gem5::GicV2::GICC_CTLR
@ GICC_CTLR
Definition: gic_v2.hh:98
gem5::GicV2::enableGrp1
Bitfield< 1 > enableGrp1
Definition: gic_v2.hh:146
gem5::GicV2::GICD_ISPENDR
static const AddrRange GICD_ISPENDR
Definition: gic_v2.hh:87
gem5::GicV2::GICC_APR0
@ GICC_APR0
Definition: gic_v2.hh:106
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::GicV2::isGroup0
bool isGroup0(ContextID ctx, uint32_t int_num)
Definition: gic_v2.hh:371
gem5::GicV2::postDelayedInt
void postDelayedInt(uint32_t cpu)
Deliver a delayed interrupt to the target CPU.
Definition: gic_v2.cc:943
base_gic.hh
gem5::GicV2::GICD_IIDR
@ GICD_IIDR
Definition: gic_v2.hh:70
gem5::GicV2::GICD_TYPER
@ GICD_TYPER
Definition: gic_v2.hh:69
gem5::GicV2::GICC_ABPR
@ GICC_ABPR
Definition: gic_v2.hh:105
gem5::GicV2::readDistributor
uint32_t readDistributor(ContextID ctx, Addr daddr) override
Definition: gic_v2.hh:523
gem5::GicV2::GICD_ICPENDR
static const AddrRange GICD_ICPENDR
Definition: gic_v2.hh:88
std::vector
STL vector class.
Definition: stl.hh:37
gem5::GicV2::cpuSgiPendingExt
uint32_t cpuSgiPendingExt[CPU_MAX]
SGI pending arrays for gem5 GIC extension mode, which instead keeps 16 SGI pending bits for each of t...
Definition: gic_v2.hh:435
gem5::GicV2::SPURIOUS_INT
static const int SPURIOUS_INT
Definition: gic_v2.hh:124
gem5::GicV2::updateRunPri
void updateRunPri()
Update the register that records priority of the highest priority active interrupt.
Definition: gic_v2.cc:837
gem5::GicV2::getBankedRegs
BankedRegs & getBankedRegs(ContextID)
Definition: gic_v2.cc:641
gem5::GicV2::DIST_SIZE
@ DIST_SIZE
Definition: gic_v2.hh:77
gem5::GicV2::GICD_PIDR3
@ GICD_PIDR3
Definition: gic_v2.hh:75
gem5::GicV2::cpuPioDelay
const Tick cpuPioDelay
Latency for a cpu operation.
Definition: gic_v2.hh:164
gem5::GicV2::bankedRegs
std::vector< BankedRegs * > bankedRegs
Definition: gic_v2.hh:217
gem5::GicV2::pendingDelayedInterrupts
int pendingDelayedInterrupts
Definition: gic_v2.hh:480
gem5::GicV2::postDelayedFiq
void postDelayedFiq(uint32_t cpu)
Definition: gic_v2.cc:969
gem5::BaseGicRegisters
Definition: base_gic.hh:127
gem5::GicV2::cpuSgiActive
uint64_t cpuSgiActive[SGI_MAX]
Definition: gic_v2.hh:430
gem5::GicV2::readCpu
Tick readCpu(PacketPtr pkt)
Handle a read to the cpu portion of the GIC.
Definition: gic_v2.cc:290
gem5::GicV2::gicdPIDR
const uint32_t gicdPIDR
Definition: gic_v2.hh:80
gem5::GicV2::BankedRegs::pendingInt
uint32_t pendingInt
GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:191
gem5::GicV2::intEnabled
uint32_t intEnabled[INT_BITS_MAX-1]
GICD_I{S,C}ENABLER{1..31} interrupt enable bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:224
gem5::GicV2::cpuEnabled
bool cpuEnabled(ContextID ctx) const
CPU enabled: Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set.
Definition: gic_v2.hh:404
gem5::GicV2::GICC_HPPIR
@ GICC_HPPIR
Definition: gic_v2.hh:104
gem5::GicV2::GICD_IGROUPR
static const AddrRange GICD_IGROUPR
Definition: gic_v2.hh:84
gem5::GicV2::intConfig
uint32_t intConfig[INT_BITS_MAX *2 - 2]
GICD_ICFGR{2...63} 2 bit per interrupt signaling if it's level or edge sensitive and if it is 1:N or ...
Definition: gic_v2.hh:308
gem5::GicV2::sendInt
void sendInt(uint32_t number) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v2.cc:866
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::GicV2::isLevelSensitive
bool isLevelSensitive(ContextID ctx, uint32_t int_num)
Definition: gic_v2.hh:359
gem5::GicV2::giccIIDR
const uint32_t giccIIDR
Definition: gic_v2.hh:82
gem5::GicV2::genSwiMask
uint64_t genSwiMask(int cpu)
generate a bit mask to check cpuSgi for an interrupt.
Definition: gic_v2.cc:721
gem5::GicV2::intNumToBit
int intNumToBit(int num) const
Definition: gic_v2.hh:461
gem5::BaseGic
Definition: base_gic.hh:72
gem5::GicV2::cpu_list
Bitfield< 23, 16 > cpu_list
Definition: gic_v2.hh:135
interrupts.hh
gem5::GicV2::getIntPriority
uint8_t & getIntPriority(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:294
gem5::GicV2::cpuSgiActiveExt
uint32_t cpuSgiActiveExt[CPU_MAX]
Definition: gic_v2.hh:436
gem5::GicV2::GICC_IAR
@ GICC_IAR
Definition: gic_v2.hh:101
gem5::GicV2::addrRanges
const AddrRangeList addrRanges
All address ranges used by this GIC.
Definition: gic_v2.hh:158
gem5::GicV2::postFiqEvent
EventFunctionWrapper * postFiqEvent[CPU_MAX]
Definition: gic_v2.hh:479
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::GicV2::GICC_IIDR
@ GICC_IIDR
Definition: gic_v2.hh:110
gem5::GicV2::GLOBAL_INT_LINES
static const int GLOBAL_INT_LINES
Definition: gic_v2.hh:127
gem5::GicV2::isFiq
bool isFiq(ContextID ctx, uint32_t int_num)
This method checks if an interrupt ID must be signaled or has been signaled as a FIQ to the cpu.
Definition: gic_v2.hh:388
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::GicV2
Definition: gic_v2.hh:62
gem5::GicV2::cpuControl
CTLR cpuControl[CPU_MAX]
GICC_CTLR: CPU interface control register.
Definition: gic_v2.hh:413
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::GicV2::haveGem5Extensions
const bool haveGem5Extensions
Are gem5 extensions available?
Definition: gic_v2.hh:174
gem5::GicV2::distPioDelay
const Tick distPioDelay
Latency for a distributor operation.
Definition: gic_v2.hh:161
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GicV2::BankedRegs::intEnabled
uint32_t intEnabled
GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:187
gem5::GicV2::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v2.cc:998
gem5::GicV2::GICD_ISENABLER
static const AddrRange GICD_ISENABLER
Definition: gic_v2.hh:85
bitunion.hh
gem5::GicV2::GICC_PMR
@ GICC_PMR
Definition: gic_v2.hh:99
gem5::GicV2::intGroup
uint32_t intGroup[INT_BITS_MAX-1]
GICD_IGROUPR{1..31} interrupt group bits for global interrupts 1b per interrupt, 32 bits per word,...
Definition: gic_v2.hh:271
gem5::GicV2::enabled
bool enabled
Gic enabled.
Definition: gic_v2.hh:171
gem5::GicV2::INT_BITS_MAX
static const int INT_BITS_MAX
Definition: gic_v2.hh:125
gem5::GicV2::updateIntState
virtual void updateIntState(int hint)
See if some processor interrupt flags need to be enabled/disabled.
Definition: gic_v2.cc:739
gem5::GicV2::getIntEnabled
uint32_t & getIntEnabled(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:227
gem5::GicV2::postFiq
void postFiq(uint32_t cpu, Tick when)
Definition: gic_v2.cc:954
gem5::GicV2::write
Tick write(PacketPtr pkt) override
A PIO read to the device, immediately split up into writeDistributor() or writeCpu()
Definition: gic_v2.cc:129
gem5::GicV2::BankedRegs
Registers "banked for each connected processor" per ARM IHI0048B.
Definition: gic_v2.hh:183
gem5::GicV2::BankedRegs::intGroup
uint32_t intGroup
GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:199
gem5::GicV2::cpu_id
Bitfield< 12, 10 > cpu_id
Definition: gic_v2.hh:141
gem5::GicV2::GICD_ICFGR
static const AddrRange GICD_ICFGR
Definition: gic_v2.hh:93
gem5::GicV2::writeCpu
Tick writeCpu(PacketPtr pkt)
Handle a write to the cpu portion of the GIC.
Definition: gic_v2.cc:560
gem5::GicV2::GICD_PIDR2
@ GICD_PIDR2
Definition: gic_v2.hh:74
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GicV2::GICD_ICENABLER
static const AddrRange GICD_ICENABLER
Definition: gic_v2.hh:86
gem5::GicV2::GICD_ISACTIVER
static const AddrRange GICD_ISACTIVER
Definition: gic_v2.hh:89
gem5::GicV2::ack_id
ack_id
Definition: gic_v2.hh:140
gem5::GicV2::read
Tick read(PacketPtr pkt) override
A PIO read to the device, immediately split up into readDistributor() or readCpu()
Definition: gic_v2.cc:115
gem5::GicV2::GICC_BPR
@ GICC_BPR
Definition: gic_v2.hh:100
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::GicV2::gem5ExtensionsEnabled
bool gem5ExtensionsEnabled
gem5 many-core extension enabled by driver
Definition: gic_v2.hh:177
gem5::GicV2::cpuPriority
uint8_t cpuPriority[CPU_MAX]
CPU priority.
Definition: gic_v2.hh:416
gem5::GicV2::GICC_APR1
@ GICC_APR1
Definition: gic_v2.hh:107
gem5::GicV2::CPU_MAX
static const int CPU_MAX
Definition: gic_v2.hh:123
platform.hh
gem5::GicV2::getCpuPriority
uint8_t getCpuPriority(unsigned cpu)
Definition: gic_v2.cc:728
gem5::GicV2::~GicV2
~GicV2()
Definition: gic_v2.cc:106
gem5::GicV2::BitUnion32
BitUnion32(SWI) Bitfield< 3
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GicV2::readDistributor
Tick readDistributor(PacketPtr pkt)
Handle a read to the distributor portion of the GIC.
Definition: gic_v2.cc:142
gem5::GicV2::cpuSgiPending
uint64_t cpuSgiPending[SGI_MAX]
One bit per cpu per software interrupt that is pending for each possible sgi source.
Definition: gic_v2.hh:429
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
addr_range.hh
gem5::GicV2::getIntConfig
uint32_t & getIntConfig(ContextID ctx, uint32_t ix)
Reads the GICD_ICFGRn register.
Definition: gic_v2.hh:317
gem5::GicV2::GICC_DIR
@ GICC_DIR
Definition: gic_v2.hh:111
gem5::GicV2::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic_v2.cc:908
gem5::GicV2::supportsVersion
bool supportsVersion(GicVersion version) override
Check if version supported.
Definition: gic_v2.cc:963
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::GicV2::cpuTarget
uint8_t cpuTarget[GLOBAL_INT_LINES]
GICD_ITARGETSR{8..255} an 8 bit cpu target id for each global interrupt.
Definition: gic_v2.hh:331
gem5::GicV2::itLines
uint32_t itLines
Number of itLines enabled.
Definition: gic_v2.hh:180
gem5::GicV2::GICD_ITARGETSR
static const AddrRange GICD_ITARGETSR
Definition: gic_v2.hh:92
gem5::GicV2::BankedRegs::intPriority
uint8_t intPriority[SGI_MAX+PPI_MAX]
GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs.
Definition: gic_v2.hh:207
gem5::GicV2::sgi_id
sgi_id
Definition: gic_v2.hh:134
gem5::GicV2::getPendingInt
uint32_t & getPendingInt(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:242
gem5::GicV2::postInt
void postInt(uint32_t cpu, Tick when)
Post an interrupt to a CPU with a delay.
Definition: gic_v2.cc:934
gem5::GicV2::GicV2
GicV2(const Params &p)
Definition: gic_v2.cc:67
gem5::GicV2::GICD_ICACTIVER
static const AddrRange GICD_ICACTIVER
Definition: gic_v2.hh:90
gem5::GicV2::list_type
Bitfield< 25, 24 > list_type
Definition: gic_v2.hh:136
gem5::GicV2::getCpuTarget
uint8_t getCpuTarget(ContextID ctx, uint32_t ix) const
Definition: gic_v2.hh:334
gem5::GicV2::BankedRegs::intConfig
uint32_t intConfig[2]
GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt.
Definition: gic_v2.hh:203
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::GicV2::gicdIIDR
const uint32_t gicdIIDR
Definition: gic_v2.hh:81
gem5::GicV2::GICD_PIDR1
@ GICD_PIDR1
Definition: gic_v2.hh:73
gem5::GicV2::intPriority
uint8_t intPriority[GLOBAL_INT_LINES]
GICD_IPRIORITYR{8..255} an 8 bit priority (lower is higher priority) for each of the global (not repl...
Definition: gic_v2.hh:291
gem5::GicV2::GICC_APR2
@ GICC_APR2
Definition: gic_v2.hh:108
gem5::GicV2::postIntEvent
EventFunctionWrapper * postIntEvent[CPU_MAX]
Definition: gic_v2.hh:478
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::GicV2::GICC_BPR_MINIMUM
static const int GICC_BPR_MINIMUM
minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); chosen for consistency with Linux...
Definition: gic_v2.hh:131
gem5::GicV2::writeDistributor
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic_v2.hh:541
gem5::GicV2::cpuBpr
uint8_t cpuBpr[CPU_MAX]
Binary point registers.
Definition: gic_v2.hh:420
gem5::GicV2::cpuRange
const EndBitUnion(CTLR) protected AddrRange cpuRange
Address range for the distributor interface.
Definition: gic_v2.hh:148
gem5::GicV2::GICD_PIDR0
@ GICD_PIDR0
Definition: gic_v2.hh:72
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< AddrRange >
gem5::GicV2::intNumToWord
int intNumToWord(int num) const
Definition: gic_v2.hh:460
gem5::GicV2::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: gic_v2.hh:494
gem5::GicV2::SGI_MASK
static const int SGI_MASK
Mask off SGI's when setting/clearing pending bits.
Definition: gic_v2.hh:118
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GicV2::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: gic_v2.cc:980
gem5::GicV2::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v2.cc:880
gem5::GicV2::NN_CONFIG_MASK
static const int NN_CONFIG_MASK
Mask for bits that config N:N mode in GICD_ICFGR's.
Definition: gic_v2.hh:121
gem5::GicV2::cpuHighestInt
uint32_t cpuHighestInt[CPU_MAX]
highest interrupt that is interrupting CPU
Definition: gic_v2.hh:423
gem5::GicV2::PPI_MAX
static const int PPI_MAX
Definition: gic_v2.hh:115

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