gem5  v22.0.0.2
gic_v2.hh
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40 
41 
46 #ifndef __DEV_ARM_GICV2_H__
47 #define __DEV_ARM_GICV2_H__
48 
49 #include <vector>
50 
51 #include "arch/arm/interrupts.hh"
52 #include "base/addr_range.hh"
53 #include "base/bitunion.hh"
54 #include "dev/arm/base_gic.hh"
55 #include "dev/io_device.hh"
56 #include "dev/platform.hh"
57 #include "params/GicV2.hh"
58 
59 namespace gem5
60 {
61 
63 {
64  public:
65  virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
66  virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
67 
68  virtual void writeDistributor(ContextID ctx, Addr daddr,
69  uint32_t data) = 0;
70  virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
71 
72  protected:
73  static void copyDistRegister(GicV2Registers* from,
75  ContextID ctx, Addr daddr);
76  static void copyCpuRegister(GicV2Registers* from,
78  ContextID ctx, Addr daddr);
79  static void copyBankedDistRange(System *sys,
80  GicV2Registers* from,
82  Addr daddr, size_t size);
83  static void clearBankedDistRange(System *sys, GicV2Registers* to,
84  Addr daddr, size_t size);
85  static void copyDistRange(GicV2Registers* from,
87  Addr daddr, size_t size);
88  static void clearDistRange(GicV2Registers* to, Addr daddr, size_t size);
89 };
90 
91 class GicV2 : public BaseGic, public GicV2Registers
92 {
93  protected:
94  // distributor memory addresses
95  enum
96  {
97  GICD_CTLR = 0x000, // control register
98  GICD_TYPER = 0x004, // controller type
99  GICD_IIDR = 0x008, // implementer id
100  GICD_SGIR = 0xf00, // software generated interrupt
101  GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
102  GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
103  GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
104  GICD_PIDR3 = 0xfec, // distributor peripheral ID3
105 
106  DIST_SIZE = 0x1000,
107  };
108 
109  const uint32_t gicdPIDR;
110  const uint32_t gicdIIDR;
111  const uint32_t giccIIDR;
112 
113  static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
114  static const AddrRange GICD_ISENABLER; // interrupt set enable
115  static const AddrRange GICD_ICENABLER; // interrupt clear enable
116  static const AddrRange GICD_ISPENDR; // set pending interrupt
117  static const AddrRange GICD_ICPENDR; // clear pending interrupt
118  static const AddrRange GICD_ISACTIVER; // active bit registers
119  static const AddrRange GICD_ICACTIVER; // clear bit registers
120  static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
121  static const AddrRange GICD_ITARGETSR; // processor target registers
122  static const AddrRange GICD_ICFGR; // interrupt config registers
123 
124  // cpu memory addresses
125  enum
126  {
127  GICC_CTLR = 0x00, // CPU control register
128  GICC_PMR = 0x04, // Interrupt priority mask
129  GICC_BPR = 0x08, // binary point register
130  GICC_IAR = 0x0C, // interrupt ack register
131  GICC_EOIR = 0x10, // end of interrupt
132  GICC_RPR = 0x14, // running priority
133  GICC_HPPIR = 0x18, // highest pending interrupt
134  GICC_ABPR = 0x1c, // aliased binary point
135  GICC_APR0 = 0xd0, // active priority register 0
136  GICC_APR1 = 0xd4, // active priority register 1
137  GICC_APR2 = 0xd8, // active priority register 2
138  GICC_APR3 = 0xdc, // active priority register 3
139  GICC_IIDR = 0xfc, // cpu interface id register
140  GICC_DIR = 0x1000, // deactive interrupt register
141  };
142 
143  static const int SGI_MAX = 16; // Number of Software Gen Interrupts
144  static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
145 
147  static const int SGI_MASK = 0xFFFF0000;
148 
150  static const int NN_CONFIG_MASK = 0x55555555;
151 
152  static const int CPU_MAX = 256; // Max number of supported CPU interfaces
153  static const int SPURIOUS_INT = 1023;
154  static const int INT_BITS_MAX = 32;
155  static const int INT_LINES_MAX = 1020;
157 
160  static const int GICC_BPR_MINIMUM = 2;
161 
162  BitUnion32(SWI)
163  Bitfield<3,0> sgi_id;
164  Bitfield<23,16> cpu_list;
165  Bitfield<25,24> list_type;
166  EndBitUnion(SWI)
167 
168  BitUnion32(IAR)
169  Bitfield<9,0> ack_id;
170  Bitfield<12,10> cpu_id;
171  EndBitUnion(IAR)
172 
173  BitUnion32(CTLR)
174  Bitfield<3> fiqEn;
175  Bitfield<1> enableGrp1;
176  Bitfield<0> enableGrp0;
178 
179  protected: /* Params */
181  const AddrRange distRange;
182 
184  const AddrRange cpuRange;
185 
188 
191 
194 
197 
198  protected:
200  bool enabled;
201 
203  const bool haveGem5Extensions;
204 
207 
209  uint32_t itLines;
210 
212  struct BankedRegs : public Serializable
213  {
216  uint32_t intEnabled;
217 
220  uint32_t pendingInt;
221 
224  uint32_t activeInt;
225 
228  uint32_t intGroup;
229 
232  uint32_t intConfig[2];
233 
237 
238  void serialize(CheckpointOut &cp) const override;
239  void unserialize(CheckpointIn &cp) override;
240 
242  intEnabled(0), pendingInt(0), activeInt(0),
243  intGroup(0), intConfig {0}, intPriority {0}
244  {}
245  };
247 
249 
254 
255  uint32_t&
256  getIntEnabled(ContextID ctx, uint32_t ix)
257  {
258  if (ix == 0) {
259  return getBankedRegs(ctx).intEnabled;
260  } else {
261  return intEnabled[ix - 1];
262  }
263  }
264 
269 
270  uint32_t&
271  getPendingInt(ContextID ctx, uint32_t ix)
272  {
273  assert(ix < INT_BITS_MAX);
274  if (ix == 0) {
275  return getBankedRegs(ctx).pendingInt;
276  } else {
277  return pendingInt[ix - 1];
278  }
279  }
280 
284  uint32_t activeInt[INT_BITS_MAX-1];
285 
286  uint32_t&
287  getActiveInt(ContextID ctx, uint32_t ix)
288  {
289  assert(ix < INT_BITS_MAX);
290  if (ix == 0) {
291  return getBankedRegs(ctx).activeInt;
292  } else {
293  return activeInt[ix - 1];
294  }
295  }
296 
300  uint32_t intGroup[INT_BITS_MAX-1];
301 
302  uint32_t&
303  getIntGroup(ContextID ctx, uint32_t ix)
304  {
305  assert(ix < INT_BITS_MAX);
306  if (ix == 0) {
307  return getBankedRegs(ctx).intGroup;
308  } else {
309  return intGroup[ix - 1];
310  }
311  }
312 
314  uint32_t iccrpr[CPU_MAX];
315 
321 
322  uint8_t&
323  getIntPriority(ContextID ctx, uint32_t ix)
324  {
325  assert(ix < INT_LINES_MAX);
326  if (ix < SGI_MAX + PPI_MAX) {
327  return getBankedRegs(ctx).intPriority[ix];
328  } else {
329  return intPriority[ix - (SGI_MAX + PPI_MAX)];
330  }
331  }
332 
337  uint32_t intConfig[INT_BITS_MAX*2 - 2];
338 
345  uint32_t&
346  getIntConfig(ContextID ctx, uint32_t ix)
347  {
348  assert(ix < INT_BITS_MAX*2);
349  if (ix < 2) {
351  return getBankedRegs(ctx).intConfig[ix];
352  } else {
353  return intConfig[ix - 2];
354  }
355  }
356 
361 
362  uint8_t
363  getCpuTarget(ContextID ctx, uint32_t ix) const
364  {
365  assert(ctx < sys->threads.numRunning());
366  assert(ix < INT_LINES_MAX);
367  if (ix < SGI_MAX + PPI_MAX) {
368  // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each
369  // field returns a value that corresponds only to the processor
370  // reading the register."
371  uint32_t ctx_mask;
372  if (gem5ExtensionsEnabled) {
373  ctx_mask = ctx;
374  } else {
375  fatal_if(ctx >= 8,
376  "%s requires the gem5_extensions parameter to support "
377  "more than 8 cores\n", name());
378  // convert the CPU id number into a bit mask
379  ctx_mask = 1 << ctx;
380  }
381  return ctx_mask;
382  } else {
383  return cpuTarget[ix - 32];
384  }
385  }
386 
387  bool
388  isLevelSensitive(ContextID ctx, uint32_t int_num)
389  {
390  if (int_num == SPURIOUS_INT) {
391  return false;
392  } else {
393  const auto ix = intNumToWord(int_num * 2);
394  const uint8_t cfg_hi = intNumToBit(int_num * 2) + 1;
395  return bits(getIntConfig(ctx, ix), cfg_hi) == 0;
396  }
397  }
398 
399  bool
400  isGroup0(ContextID ctx, uint32_t int_num)
401  {
402  const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
403  return !bits(group_reg, intNumToBit(int_num));
404  }
405 
416  bool
417  isFiq(ContextID ctx, uint32_t int_num)
418  {
419  const bool is_group0 = isGroup0(ctx, int_num);
420  const bool use_fiq = cpuControl[ctx].fiqEn;
421 
422  if (is_group0 && use_fiq) {
423  return true;
424  } else {
425  return false;
426  }
427  }
428 
432  bool
434  {
435  return cpuControl[ctx].enableGrp0 ||
436  cpuControl[ctx].enableGrp1;
437  }
438 
443 
446  uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
447 
449  uint8_t cpuBpr[CPU_MAX];
450 
453 
460 
466 
471 
475  void softInt(ContextID ctx, SWI swi);
476 
480  void updateIntState(int hint);
481 
484  void updateRunPri();
485 
487  uint64_t genSwiMask(int cpu);
488 
489  int intNumToWord(int num) const { return num >> 5; }
490  int intNumToBit(int num) const { return num % 32; }
491 
493  void clearInt(ContextID ctx, uint32_t int_num);
494 
498  void postInt(uint32_t cpu, Tick when);
499  void postFiq(uint32_t cpu, Tick when);
500 
504  void postDelayedInt(uint32_t cpu);
505  void postDelayedFiq(uint32_t cpu);
506 
510 
511  public:
512  using Params = GicV2Params;
513  GicV2(const Params &p);
514  ~GicV2();
515 
516  DrainState drain() override;
517  void drainResume() override;
518 
519  void serialize(CheckpointOut &cp) const override;
520  void unserialize(CheckpointIn &cp) override;
521 
522  public: /* PioDevice */
523  AddrRangeList getAddrRanges() const override { return addrRanges; }
524 
528  Tick read(PacketPtr pkt) override;
529 
533  Tick write(PacketPtr pkt) override;
534 
535  public: /* BaseGic */
536  void sendInt(uint32_t number) override;
537  void clearInt(uint32_t number) override;
538 
539  void sendPPInt(uint32_t num, uint32_t cpu) override;
540  void clearPPInt(uint32_t num, uint32_t cpu) override;
541 
542  bool supportsVersion(GicVersion version) override;
543 
544  protected:
546 
551  uint32_t readDistributor(ContextID ctx, Addr daddr,
552  size_t resp_sz);
553  uint32_t
554  readDistributor(ContextID ctx, Addr daddr) override
555  {
556  return readDistributor(ctx, daddr, 4);
557  }
558 
562  Tick readCpu(PacketPtr pkt);
563  uint32_t readCpu(ContextID ctx, Addr daddr) override;
564 
569  void writeDistributor(ContextID ctx, Addr daddr,
570  uint32_t data, size_t data_sz);
571  void
572  writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
573  {
574  return writeDistributor(ctx, daddr, data, 4);
575  }
576 
580  Tick writeCpu(PacketPtr pkt);
581  void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
582 };
583 
584 } // namespace gem5
585 
586 #endif //__DEV_ARM_GIC_H__
gem5::GicV2::clearInt
void clearInt(ContextID ctx, uint32_t int_num)
Clears a cpu IRQ or FIQ signal.
Definition: gic_v2.cc:981
gem5::GicV2::BankedRegs::BankedRegs
BankedRegs()
Definition: gic_v2.hh:241
gem5::GicV2::GICC_PMR
@ GICC_PMR
Definition: gic_v2.hh:128
gem5::GicV2::BankedRegs::activeInt
uint32_t activeInt
GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:224
gem5::GicV2::EndBitUnion
EndBitUnion(SWI) BitUnion32(IAR) Bitfield< 9
gem5::GicV2::iccrpr
uint32_t iccrpr[CPU_MAX]
read only running priority register, 1 per cpu
Definition: gic_v2.hh:314
gem5::GicV2::GICC_BPR
@ GICC_BPR
Definition: gic_v2.hh:129
gem5::GicV2::GICC_EOIR
@ GICC_EOIR
Definition: gic_v2.hh:131
gem5::GicV2::GICC_APR0
@ GICC_APR0
Definition: gic_v2.hh:135
gem5::GicV2::DIST_SIZE
@ DIST_SIZE
Definition: gic_v2.hh:106
io_device.hh
gem5::GicV2::SGI_MAX
static const int SGI_MAX
Definition: gic_v2.hh:143
gem5::GicV2::GICD_IPRIORITYR
static const AddrRange GICD_IPRIORITYR
Definition: gic_v2.hh:120
gem5::GicV2::intLatency
const Tick intLatency
Latency for a interrupt to get to CPU.
Definition: gic_v2.hh:196
gem5::GicV2Registers::copyCpuRegister
static void copyCpuRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr)
Definition: gic_v2.cc:78
gem5::GicV2::writeDistributor
Tick writeDistributor(PacketPtr pkt)
Handle a write to the distributor portion of the GIC.
Definition: gic_v2.cc:444
gem5::GicV2::cpuPpiPending
uint32_t cpuPpiPending[CPU_MAX]
One bit per private peripheral interrupt.
Definition: gic_v2.hh:469
gem5::GicV2::enableGrp0
Bitfield< 0 > enableGrp0
Definition: gic_v2.hh:176
gem5::GicV2::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gic_v2.cc:1173
gem5::GicV2::activeInt
uint32_t activeInt[INT_BITS_MAX-1]
GICD_I{S,C}ACTIVER{1..31} interrupt active bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:284
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::GicV2::softInt
void softInt(ContextID ctx, SWI swi)
software generated interrupt
Definition: gic_v2.cc:706
gem5::GicV2::getActiveInt
uint32_t & getActiveInt(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:287
gem5::GicV2::getIntGroup
uint32_t & getIntGroup(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:303
gem5::GicV2::pendingInt
uint32_t pendingInt[INT_BITS_MAX-1]
GICD_I{S,C}PENDR{1..31} interrupt pending bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:268
gem5::GicV2::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: gic_v2.cc:1049
gem5::GicV2::cpuPpiActive
uint32_t cpuPpiActive[CPU_MAX]
Definition: gic_v2.hh:470
gem5::GicV2::INT_LINES_MAX
static const int INT_LINES_MAX
Definition: gic_v2.hh:155
gem5::GicV2::enableGrp1
Bitfield< 1 > enableGrp1
Definition: gic_v2.hh:175
gem5::GicV2Registers::clearBankedDistRange
static void clearBankedDistRange(System *sys, GicV2Registers *to, Addr daddr, size_t size)
Definition: gic_v2.cc:98
gem5::GicV2::GICD_ISPENDR
static const AddrRange GICD_ISPENDR
Definition: gic_v2.hh:116
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::GicV2::isGroup0
bool isGroup0(ContextID ctx, uint32_t int_num)
Definition: gic_v2.hh:400
gem5::GicV2::postDelayedInt
void postDelayedInt(uint32_t cpu)
Deliver a delayed interrupt to the target CPU.
Definition: gic_v2.cc:1001
gem5::GicV2::GICD_PIDR2
@ GICD_PIDR2
Definition: gic_v2.hh:103
base_gic.hh
gem5::GicV2Registers::clearDistRange
static void clearDistRange(GicV2Registers *to, Addr daddr, size_t size)
Definition: gic_v2.cc:116
gem5::GicV2::readDistributor
uint32_t readDistributor(ContextID ctx, Addr daddr) override
Definition: gic_v2.hh:554
gem5::GicV2::GICD_SGIR
@ GICD_SGIR
Definition: gic_v2.hh:100
gem5::GicV2::GICD_ICPENDR
static const AddrRange GICD_ICPENDR
Definition: gic_v2.hh:117
std::vector
STL vector class.
Definition: stl.hh:37
gem5::GicV2::GICC_IIDR
@ GICC_IIDR
Definition: gic_v2.hh:139
gem5::GicV2::cpuSgiPendingExt
uint32_t cpuSgiPendingExt[CPU_MAX]
SGI pending arrays for gem5 GIC extension mode, which instead keeps 16 SGI pending bits for each of t...
Definition: gic_v2.hh:464
gem5::GicV2::SPURIOUS_INT
static const int SPURIOUS_INT
Definition: gic_v2.hh:153
gem5::GicV2::GICC_APR1
@ GICC_APR1
Definition: gic_v2.hh:136
gem5::GicV2::updateRunPri
void updateRunPri()
Update the register that records priority of the highest priority active interrupt.
Definition: gic_v2.cc:895
gem5::GicV2::getBankedRegs
BankedRegs & getBankedRegs(ContextID)
Definition: gic_v2.cc:696
gem5::GicV2Registers::readCpu
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
gem5::GicV2::cpuPioDelay
const Tick cpuPioDelay
Latency for a cpu operation.
Definition: gic_v2.hh:193
gem5::GicV2::bankedRegs
std::vector< BankedRegs * > bankedRegs
Definition: gic_v2.hh:246
gem5::GicV2::pendingDelayedInterrupts
int pendingDelayedInterrupts
Definition: gic_v2.hh:509
gem5::GicV2::postDelayedFiq
void postDelayedFiq(uint32_t cpu)
Definition: gic_v2.cc:1027
gem5::GicV2::cpuSgiActive
uint64_t cpuSgiActive[SGI_MAX]
Definition: gic_v2.hh:459
gem5::GicV2::readCpu
Tick readCpu(PacketPtr pkt)
Handle a read to the cpu portion of the GIC.
Definition: gic_v2.cc:345
gem5::GicV2::gicdPIDR
const uint32_t gicdPIDR
Definition: gic_v2.hh:109
gem5::GicV2::BankedRegs::pendingInt
uint32_t pendingInt
GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:220
gem5::GicV2Registers
Definition: gic_v2.hh:62
gem5::GicV2::intEnabled
uint32_t intEnabled[INT_BITS_MAX-1]
GICD_I{S,C}ENABLER{1..31} interrupt enable bits for global interrupts 1b per interrupt,...
Definition: gic_v2.hh:253
gem5::GicV2::cpuEnabled
bool cpuEnabled(ContextID ctx) const
CPU enabled: Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set.
Definition: gic_v2.hh:433
gem5::GicV2::GICD_IGROUPR
static const AddrRange GICD_IGROUPR
Definition: gic_v2.hh:113
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::GicV2::GICC_APR3
@ GICC_APR3
Definition: gic_v2.hh:138
gem5::GicV2::intConfig
uint32_t intConfig[INT_BITS_MAX *2 - 2]
GICD_ICFGR{2...63} 2 bit per interrupt signaling if it's level or edge sensitive and if it is 1:N or ...
Definition: gic_v2.hh:337
gem5::GicV2::sendInt
void sendInt(uint32_t number) override
Post an interrupt from a device that is connected to the GIC.
Definition: gic_v2.cc:924
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::GicV2Registers::copyBankedDistRange
static void copyBankedDistRange(System *sys, GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size)
Definition: gic_v2.cc:88
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::GicV2::isLevelSensitive
bool isLevelSensitive(ContextID ctx, uint32_t int_num)
Definition: gic_v2.hh:388
gem5::GicV2::giccIIDR
const uint32_t giccIIDR
Definition: gic_v2.hh:111
gem5::GicV2::GICD_CTLR
@ GICD_CTLR
Definition: gic_v2.hh:97
gem5::GicV2::genSwiMask
uint64_t genSwiMask(int cpu)
generate a bit mask to check cpuSgi for an interrupt.
Definition: gic_v2.cc:776
gem5::System
Definition: system.hh:75
gem5::GicV2::intNumToBit
int intNumToBit(int num) const
Definition: gic_v2.hh:490
gem5::BaseGic
Definition: base_gic.hh:72
gem5::GicV2::cpu_list
Bitfield< 23, 16 > cpu_list
Definition: gic_v2.hh:164
interrupts.hh
gem5::GicV2::getIntPriority
uint8_t & getIntPriority(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:323
gem5::GicV2::GICC_HPPIR
@ GICC_HPPIR
Definition: gic_v2.hh:133
gem5::GicV2::cpuSgiActiveExt
uint32_t cpuSgiActiveExt[CPU_MAX]
Definition: gic_v2.hh:465
gem5::GicV2::addrRanges
const AddrRangeList addrRanges
All address ranges used by this GIC.
Definition: gic_v2.hh:187
gem5::GicV2::GICC_DIR
@ GICC_DIR
Definition: gic_v2.hh:140
gem5::GicV2::postFiqEvent
EventFunctionWrapper * postFiqEvent[CPU_MAX]
Definition: gic_v2.hh:508
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::GicV2::GICC_IAR
@ GICC_IAR
Definition: gic_v2.hh:130
gem5::GicV2::GLOBAL_INT_LINES
static const int GLOBAL_INT_LINES
Definition: gic_v2.hh:156
gem5::GicV2::isFiq
bool isFiq(ContextID ctx, uint32_t int_num)
This method checks if an interrupt ID must be signaled or has been signaled as a FIQ to the cpu.
Definition: gic_v2.hh:417
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::GicV2
Definition: gic_v2.hh:91
gem5::GicV2::cpuControl
CTLR cpuControl[CPU_MAX]
GICC_CTLR: CPU interface control register.
Definition: gic_v2.hh:442
gem5::GicV2::haveGem5Extensions
const bool haveGem5Extensions
Are gem5 extensions available?
Definition: gic_v2.hh:203
gem5::GicV2::distPioDelay
const Tick distPioDelay
Latency for a distributor operation.
Definition: gic_v2.hh:190
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GicV2::BankedRegs::intEnabled
uint32_t intEnabled
GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:216
gem5::GicV2::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gic_v2.cc:1128
gem5::GicV2::GICD_ISENABLER
static const AddrRange GICD_ISENABLER
Definition: gic_v2.hh:114
bitunion.hh
gem5::GicV2::GICD_TYPER
@ GICD_TYPER
Definition: gic_v2.hh:98
gem5::GicV2::intGroup
uint32_t intGroup[INT_BITS_MAX-1]
GICD_IGROUPR{1..31} interrupt group bits for global interrupts 1b per interrupt, 32 bits per word,...
Definition: gic_v2.hh:300
gem5::GicV2::enabled
bool enabled
Gic enabled.
Definition: gic_v2.hh:200
gem5::GicV2::INT_BITS_MAX
static const int INT_BITS_MAX
Definition: gic_v2.hh:154
gem5::GicV2::updateIntState
void updateIntState(int hint)
See if some processor interrupt flags need to be enabled/disabled.
Definition: gic_v2.cc:794
gem5::GicV2::getIntEnabled
uint32_t & getIntEnabled(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:256
gem5::GicV2::postFiq
void postFiq(uint32_t cpu, Tick when)
Definition: gic_v2.cc:1012
gem5::GicV2::write
Tick write(PacketPtr pkt) override
A PIO read to the device, immediately split up into writeDistributor() or writeCpu()
Definition: gic_v2.cc:184
gem5::GicV2::BankedRegs
Registers "banked for each connected processor" per ARM IHI0048B.
Definition: gic_v2.hh:212
gem5::GicV2::BankedRegs::intGroup
uint32_t intGroup
GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt.
Definition: gic_v2.hh:228
gem5::GicV2::cpu_id
Bitfield< 12, 10 > cpu_id
Definition: gic_v2.hh:170
gem5::GicV2::GICD_ICFGR
static const AddrRange GICD_ICFGR
Definition: gic_v2.hh:122
gem5::GicV2::GICD_IIDR
@ GICD_IIDR
Definition: gic_v2.hh:99
gem5::GicV2::writeCpu
Tick writeCpu(PacketPtr pkt)
Handle a write to the cpu portion of the GIC.
Definition: gic_v2.cc:615
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::GicV2::GICD_ICENABLER
static const AddrRange GICD_ICENABLER
Definition: gic_v2.hh:115
gem5::GicV2::GICD_ISACTIVER
static const AddrRange GICD_ISACTIVER
Definition: gic_v2.hh:118
gem5::GicV2::ack_id
ack_id
Definition: gic_v2.hh:169
gem5::GicV2::read
Tick read(PacketPtr pkt) override
A PIO read to the device, immediately split up into readDistributor() or readCpu()
Definition: gic_v2.cc:170
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::GicV2::GICC_APR2
@ GICC_APR2
Definition: gic_v2.hh:137
gem5::GicV2::gem5ExtensionsEnabled
bool gem5ExtensionsEnabled
gem5 many-core extension enabled by driver
Definition: gic_v2.hh:206
gem5::GicV2::cpuPriority
uint8_t cpuPriority[CPU_MAX]
CPU priority.
Definition: gic_v2.hh:445
gem5::GicV2::CPU_MAX
static const int CPU_MAX
Definition: gic_v2.hh:152
platform.hh
gem5::GicV2::getCpuPriority
uint8_t getCpuPriority(unsigned cpu)
Definition: gic_v2.cc:783
gem5::GicV2::~GicV2
~GicV2()
Definition: gic_v2.cc:161
gem5::GicV2::BitUnion32
BitUnion32(SWI) Bitfield< 3
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GicV2::readDistributor
Tick readDistributor(PacketPtr pkt)
Handle a read to the distributor portion of the GIC.
Definition: gic_v2.cc:197
gem5::GicV2::cpuSgiPending
uint64_t cpuSgiPending[SGI_MAX]
One bit per cpu per software interrupt that is pending for each possible sgi source.
Definition: gic_v2.hh:458
gem5::GicV2::copyGicState
void copyGicState(GicV2Registers *from, GicV2Registers *to)
GIC state transfer.
Definition: gic_v2.cc:1056
gem5::GicV2Registers::copyDistRange
static void copyDistRange(GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size)
Definition: gic_v2.cc:107
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
addr_range.hh
gem5::GicV2::getIntConfig
uint32_t & getIntConfig(ContextID ctx, uint32_t ix)
Reads the GICD_ICFGRn register.
Definition: gic_v2.hh:346
gem5::GicV2::clearPPInt
void clearPPInt(uint32_t num, uint32_t cpu) override
Definition: gic_v2.cc:966
gem5::GicV2::supportsVersion
bool supportsVersion(GicVersion version) override
Check if version supported.
Definition: gic_v2.cc:1021
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::GicV2::cpuTarget
uint8_t cpuTarget[GLOBAL_INT_LINES]
GICD_ITARGETSR{8..255} an 8 bit cpu target id for each global interrupt.
Definition: gic_v2.hh:360
gem5::GicV2::itLines
uint32_t itLines
Number of itLines enabled.
Definition: gic_v2.hh:209
gem5::GicV2::GICD_ITARGETSR
static const AddrRange GICD_ITARGETSR
Definition: gic_v2.hh:121
gem5::GicV2::GICC_CTLR
@ GICC_CTLR
Definition: gic_v2.hh:127
gem5::GicV2Registers::copyDistRegister
static void copyDistRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr)
Definition: gic_v2.cc:68
gem5::GicV2::BankedRegs::intPriority
uint8_t intPriority[SGI_MAX+PPI_MAX]
GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs.
Definition: gic_v2.hh:236
gem5::GicV2::GICC_ABPR
@ GICC_ABPR
Definition: gic_v2.hh:134
gem5::GicV2::sgi_id
sgi_id
Definition: gic_v2.hh:163
gem5::GicV2::getPendingInt
uint32_t & getPendingInt(ContextID ctx, uint32_t ix)
Definition: gic_v2.hh:271
gem5::GicV2Registers::readDistributor
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
gem5::GicV2::postInt
void postInt(uint32_t cpu, Tick when)
Post an interrupt to a CPU with a delay.
Definition: gic_v2.cc:992
gem5::GicV2::GicV2
GicV2(const Params &p)
Definition: gic_v2.cc:122
gem5::GicV2::GICD_PIDR1
@ GICD_PIDR1
Definition: gic_v2.hh:102
gem5::GicV2::GICD_ICACTIVER
static const AddrRange GICD_ICACTIVER
Definition: gic_v2.hh:119
gem5::GicV2::list_type
Bitfield< 25, 24 > list_type
Definition: gic_v2.hh:165
gem5::GicV2::getCpuTarget
uint8_t getCpuTarget(ContextID ctx, uint32_t ix) const
Definition: gic_v2.hh:363
gem5::GicV2::BankedRegs::intConfig
uint32_t intConfig[2]
GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt.
Definition: gic_v2.hh:232
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::GicV2::gicdIIDR
const uint32_t gicdIIDR
Definition: gic_v2.hh:110
gem5::GicV2::intPriority
uint8_t intPriority[GLOBAL_INT_LINES]
GICD_IPRIORITYR{8..255} an 8 bit priority (lower is higher priority) for each of the global (not repl...
Definition: gic_v2.hh:320
gem5::GicV2Registers::writeCpu
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data)=0
gem5::GicV2::postIntEvent
EventFunctionWrapper * postIntEvent[CPU_MAX]
Definition: gic_v2.hh:507
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::GicV2::GICC_BPR_MINIMUM
static const int GICC_BPR_MINIMUM
minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); chosen for consistency with Linux...
Definition: gic_v2.hh:160
gem5::GicV2::writeDistributor
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
Definition: gic_v2.hh:572
gem5::GicV2::cpuBpr
uint8_t cpuBpr[CPU_MAX]
Binary point registers.
Definition: gic_v2.hh:449
gem5::GicV2::cpuRange
const EndBitUnion(CTLR) protected AddrRange cpuRange
Address range for the distributor interface.
Definition: gic_v2.hh:177
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
std::list< AddrRange >
gem5::GicV2::intNumToWord
int intNumToWord(int num) const
Definition: gic_v2.hh:489
gem5::GicV2::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: gic_v2.hh:523
gem5::GicV2::SGI_MASK
static const int SGI_MASK
Mask off SGI's when setting/clearing pending bits.
Definition: gic_v2.hh:147
gem5::GicV2::GICD_PIDR0
@ GICD_PIDR0
Definition: gic_v2.hh:101
gem5::GicV2::GICD_PIDR3
@ GICD_PIDR3
Definition: gic_v2.hh:104
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::GicV2::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: gic_v2.cc:1038
gem5::GicV2::sendPPInt
void sendPPInt(uint32_t num, uint32_t cpu) override
Interface call for private peripheral interrupts.
Definition: gic_v2.cc:938
gem5::GicV2::GICC_RPR
@ GICC_RPR
Definition: gic_v2.hh:132
gem5::GicV2::NN_CONFIG_MASK
static const int NN_CONFIG_MASK
Mask for bits that config N:N mode in GICD_ICFGR's.
Definition: gic_v2.hh:150
gem5::GicV2::cpuHighestInt
uint32_t cpuHighestInt[CPU_MAX]
highest interrupt that is interrupting CPU
Definition: gic_v2.hh:452
gem5::GicV2Registers::writeDistributor
virtual void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)=0
gem5::GicV2::PPI_MAX
static const int PPI_MAX
Definition: gic_v2.hh:144

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