46 #ifndef __DEV_ARM_GICV2_H__
47 #define __DEV_ARM_GICV2_H__
57 #include "params/GicV2.hh"
82 Addr daddr,
size_t size);
84 Addr daddr,
size_t size);
87 Addr daddr,
size_t size);
365 assert(ctx < sys->threads.numRunning());
376 "%s requires the gem5_extensions parameter to support "
377 "more than 8 cores\n",
name());
394 const uint8_t cfg_hi =
intNumToBit(int_num * 2) + 1;
419 const bool is_group0 =
isGroup0(ctx, int_num);
422 if (is_group0 && use_fiq) {
536 void sendInt(uint32_t number)
override;
537 void clearInt(uint32_t number)
override;
539 void sendPPInt(uint32_t num, uint32_t cpu)
override;
540 void clearPPInt(uint32_t num, uint32_t cpu)
override;
570 uint32_t
data,
size_t data_sz);
Base class for ARM GIC implementations.
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
static void clearDistRange(GicV2Registers *to, Addr daddr, size_t size)
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
static void copyDistRange(GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size)
virtual void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)=0
static void copyBankedDistRange(System *sys, GicV2Registers *from, GicV2Registers *to, Addr daddr, size_t size)
static void copyDistRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr)
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data)=0
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
static void clearBankedDistRange(System *sys, GicV2Registers *to, Addr daddr, size_t size)
static void copyCpuRegister(GicV2Registers *from, GicV2Registers *to, ContextID ctx, Addr daddr)
static const int GLOBAL_INT_LINES
const Tick distPioDelay
Latency for a distributor operation.
std::vector< BankedRegs * > bankedRegs
int intNumToBit(int num) const
EventFunctionWrapper * postIntEvent[CPU_MAX]
uint32_t itLines
Number of itLines enabled.
static const AddrRange GICD_IPRIORITYR
bool isFiq(ContextID ctx, uint32_t int_num)
This method checks if an interrupt ID must be signaled or has been signaled as a FIQ to the cpu.
static const AddrRange GICD_ICACTIVER
void postFiq(uint32_t cpu, Tick when)
uint32_t intEnabled[INT_BITS_MAX-1]
GICD_I{S,C}ENABLER{1..31} interrupt enable bits for global interrupts 1b per interrupt,...
uint32_t cpuSgiPendingExt[CPU_MAX]
SGI pending arrays for gem5 GIC extension mode, which instead keeps 16 SGI pending bits for each of t...
static const AddrRange GICD_ICFGR
static const AddrRange GICD_ICENABLER
static const int INT_LINES_MAX
void softInt(ContextID ctx, SWI swi)
software generated interrupt
uint64_t cpuSgiPending[SGI_MAX]
One bit per cpu per software interrupt that is pending for each possible sgi source.
uint32_t & getActiveInt(ContextID ctx, uint32_t ix)
static const AddrRange GICD_ISPENDR
Tick readDistributor(PacketPtr pkt)
Handle a read to the distributor portion of the GIC.
EndBitUnion(CTLR) protected const AddrRange cpuRange
Address range for the distributor interface.
Bitfield< 12, 10 > cpu_id
Tick writeDistributor(PacketPtr pkt)
Handle a write to the distributor portion of the GIC.
uint8_t cpuPriority[CPU_MAX]
CPU priority.
int pendingDelayedInterrupts
uint32_t pendingInt[INT_BITS_MAX-1]
GICD_I{S,C}PENDR{1..31} interrupt pending bits for global interrupts 1b per interrupt,...
uint32_t & getIntGroup(ContextID ctx, uint32_t ix)
BankedRegs & getBankedRegs(ContextID)
static const int INT_BITS_MAX
void copyGicState(GicV2Registers *from, GicV2Registers *to)
GIC state transfer.
EndBitUnion(SWI) BitUnion32(IAR) Bitfield< 9
void postDelayedFiq(uint32_t cpu)
EventFunctionWrapper * postFiqEvent[CPU_MAX]
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data) override
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
uint32_t cpuPpiActive[CPU_MAX]
static const AddrRange GICD_ISACTIVER
static const AddrRange GICD_IGROUPR
uint8_t getCpuPriority(unsigned cpu)
int intNumToWord(int num) const
void drainResume() override
Resume execution after a successful drain.
static const int SGI_MASK
Mask off SGI's when setting/clearing pending bits.
uint32_t intGroup[INT_BITS_MAX-1]
GICD_IGROUPR{1..31} interrupt group bits for global interrupts 1b per interrupt, 32 bits per word,...
uint32_t intConfig[INT_BITS_MAX *2 - 2]
GICD_ICFGR{2...63} 2 bit per interrupt signaling if it's level or edge sensitive and if it is 1:N or ...
const Tick intLatency
Latency for a interrupt to get to CPU.
void updateIntState(int hint)
See if some processor interrupt flags need to be enabled/disabled.
BitUnion32(SWI) Bitfield< 3
Tick readCpu(PacketPtr pkt)
Handle a read to the cpu portion of the GIC.
const bool haveGem5Extensions
Are gem5 extensions available?
bool isLevelSensitive(ContextID ctx, uint32_t int_num)
Tick write(PacketPtr pkt) override
A PIO read to the device, immediately split up into writeDistributor() or writeCpu()
void sendPPInt(uint32_t num, uint32_t cpu) override
Interface call for private peripheral interrupts.
static const int GICC_BPR_MINIMUM
minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); chosen for consistency with Linux...
uint32_t & getPendingInt(ContextID ctx, uint32_t ix)
uint8_t cpuBpr[CPU_MAX]
Binary point registers.
uint64_t cpuSgiActive[SGI_MAX]
Bitfield< 25, 24 > list_type
Tick writeCpu(PacketPtr pkt)
Handle a write to the cpu portion of the GIC.
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
CTLR cpuControl[CPU_MAX]
GICC_CTLR: CPU interface control register.
void updateRunPri()
Update the register that records priority of the highest priority active interrupt.
uint32_t cpuSgiActiveExt[CPU_MAX]
static const AddrRange GICD_ISENABLER
void sendInt(uint32_t number) override
Post an interrupt from a device that is connected to the GIC.
uint32_t cpuPpiPending[CPU_MAX]
One bit per private peripheral interrupt.
uint32_t cpuHighestInt[CPU_MAX]
highest interrupt that is interrupting CPU
Tick read(PacketPtr pkt) override
A PIO read to the device, immediately split up into readDistributor() or readCpu()
uint8_t cpuTarget[GLOBAL_INT_LINES]
GICD_ITARGETSR{8..255} an 8 bit cpu target id for each global interrupt.
bool cpuEnabled(ContextID ctx) const
CPU enabled: Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set.
void serialize(CheckpointOut &cp) const override
Serialize an object.
uint64_t genSwiMask(int cpu)
generate a bit mask to check cpuSgi for an interrupt.
static const int SPURIOUS_INT
static const int NN_CONFIG_MASK
Mask for bits that config N:N mode in GICD_ICFGR's.
bool supportsVersion(GicVersion version) override
Check if version supported.
const AddrRangeList addrRanges
All address ranges used by this GIC.
void clearPPInt(uint32_t num, uint32_t cpu) override
bool gem5ExtensionsEnabled
gem5 many-core extension enabled by driver
uint32_t & getIntConfig(ContextID ctx, uint32_t ix)
Reads the GICD_ICFGRn register.
const Tick cpuPioDelay
Latency for a cpu operation.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
uint32_t & getIntEnabled(ContextID ctx, uint32_t ix)
uint8_t getCpuTarget(ContextID ctx, uint32_t ix) const
static const AddrRange GICD_ITARGETSR
Bitfield< 23, 16 > cpu_list
uint32_t readDistributor(ContextID ctx, Addr daddr) override
uint8_t intPriority[GLOBAL_INT_LINES]
GICD_IPRIORITYR{8..255} an 8 bit priority (lower is higher priority) for each of the global (not repl...
void clearInt(ContextID ctx, uint32_t int_num)
Clears a cpu IRQ or FIQ signal.
void postInt(uint32_t cpu, Tick when)
Post an interrupt to a CPU with a delay.
uint32_t activeInt[INT_BITS_MAX-1]
GICD_I{S,C}ACTIVER{1..31} interrupt active bits for global interrupts 1b per interrupt,...
uint32_t iccrpr[CPU_MAX]
read only running priority register, 1 per cpu
void postDelayedInt(uint32_t cpu)
Deliver a delayed interrupt to the target CPU.
bool isGroup0(ContextID ctx, uint32_t int_num)
static const AddrRange GICD_ICPENDR
uint8_t & getIntPriority(ContextID ctx, uint32_t ix)
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Basic support for object serialization.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
DrainState
Object drain/handover states.
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
int ContextID
Globally unique thread context ID.
Registers "banked for each connected processor" per ARM IHI0048B.
uint32_t intEnabled
GICD_I{S,C}ENABLER0 interrupt enable bits for first 32 interrupts, 1b per interrupt.
uint32_t intGroup
GICD_IGROUPR0 interrupt group bits for first 32 interrupts, 1b per interrupt.
uint32_t activeInt
GICD_I{S,C}ACTIVER0 interrupt active bits for first 32 interrupts, 1b per interrupt.
uint8_t intPriority[SGI_MAX+PPI_MAX]
GICD_IPRIORITYR{0..7} interrupt priority for SGIs and PPIs.
uint32_t pendingInt
GICD_I{S,C}PENDR0 interrupt pending bits for first 32 interrupts, 1b per interrupt.
uint32_t intConfig[2]
GICD_ICFGR0, GICD_ICFGR1 interrupt config bits for first 32 interrupts, 2b per interrupt.