#include <gic_v2.hh>

Inheritance diagram for gem5::GicV2:

Classes
struct	BankedRegs
	Registers "banked for each connected processor" per ARM IHI0048B. More...

Public Types
using	Params = GicV2Params

Public Types inherited from gem5::BaseGic
enum class	GicVersion { GIC_V2 , GIC_V3 , GIC_V4 }

typedef BaseGicParams	Params

Public Types inherited from gem5::PioDevice
using	Params = PioDeviceParams

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	GicV2 (const Params &p)

	~GicV2 ()

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. More...

void	drainResume () override
	Resume execution after a successful drain. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

AddrRangeList	getAddrRanges () const override
	Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to. More...

Tick	read (PacketPtr pkt) override
	A PIO read to the device, immediately split up into readDistributor() or readCpu() More...

Tick	write (PacketPtr pkt) override
	A PIO read to the device, immediately split up into writeDistributor() or writeCpu() More...

void	sendInt (uint32_t number) override
	Post an interrupt from a device that is connected to the GIC. More...

void	clearInt (uint32_t number) override
	Clear an interrupt from a device that is connected to the GIC. More...

void	sendPPInt (uint32_t num, uint32_t cpu) override
	Interface call for private peripheral interrupts. More...

void	clearPPInt (uint32_t num, uint32_t cpu) override

bool	supportsVersion (GicVersion version) override
	Check if version supported. More...

Public Member Functions inherited from gem5::BaseGic
	BaseGic (const Params &p)

virtual	~BaseGic ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

const Params &	params () const

ArmSystem *	getSystem () const

Public Member Functions inherited from gem5::PioDevice
	PioDevice (const Params &p)

virtual	~PioDevice ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Types
enum	{ GICD_CTLR = 0x000 , GICD_TYPER = 0x004 , GICD_IIDR = 0x008 , GICD_SGIR = 0xf00 , GICD_PIDR0 = 0xfe0 , GICD_PIDR1 = 0xfe4 , GICD_PIDR2 = 0xfe8 , GICD_PIDR3 = 0xfec , DIST_SIZE = 0x1000 }

enum	{ GICC_CTLR = 0x00 , GICC_PMR = 0x04 , GICC_BPR = 0x08 , GICC_IAR = 0x0C , GICC_EOIR = 0x10 , GICC_RPR = 0x14 , GICC_HPPIR = 0x18 , GICC_ABPR = 0x1c , GICC_APR0 = 0xd0 , GICC_APR1 = 0xd4 , GICC_APR2 = 0xd8 , GICC_APR3 = 0xdc , GICC_IIDR = 0xfc , GICC_DIR = 0x1000 }

Protected Member Functions
	BitUnion32 (SWI) Bitfield< 3

	EndBitUnion (SWI) BitUnion32(IAR) Bitfield< 9

	EndBitUnion (IAR) BitUnion32(CTLR) Bitfield< 3 > fiqEn

BankedRegs &	getBankedRegs (ContextID)

uint32_t &	getIntEnabled (ContextID ctx, uint32_t ix)

uint32_t &	getPendingInt (ContextID ctx, uint32_t ix)

uint32_t &	getActiveInt (ContextID ctx, uint32_t ix)

uint32_t &	getIntGroup (ContextID ctx, uint32_t ix)

uint8_t &	getIntPriority (ContextID ctx, uint32_t ix)

uint32_t &	getIntConfig (ContextID ctx, uint32_t ix)
	Reads the GICD_ICFGRn register. More...

uint8_t	getCpuTarget (ContextID ctx, uint32_t ix) const

bool	isLevelSensitive (ContextID ctx, uint32_t int_num)

bool	isGroup0 (ContextID ctx, uint32_t int_num)

bool	isFiq (ContextID ctx, uint32_t int_num)
	This method checks if an interrupt ID must be signaled or has been signaled as a FIQ to the cpu. More...

bool	cpuEnabled (ContextID ctx) const
	CPU enabled: Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set. More...

uint8_t	getCpuPriority (unsigned cpu)

void	softInt (ContextID ctx, SWI swi)
	software generated interrupt More...

void	updateIntState (int hint)
	See if some processor interrupt flags need to be enabled/disabled. More...

void	updateRunPri ()
	Update the register that records priority of the highest priority active interrupt. More...

uint64_t	genSwiMask (int cpu)
	generate a bit mask to check cpuSgi for an interrupt. More...

int	intNumToWord (int num) const

int	intNumToBit (int num) const

void	clearInt (ContextID ctx, uint32_t int_num)
	Clears a cpu IRQ or FIQ signal. More...

void	postInt (uint32_t cpu, Tick when)
	Post an interrupt to a CPU with a delay. More...

void	postFiq (uint32_t cpu, Tick when)

void	postDelayedInt (uint32_t cpu)
	Deliver a delayed interrupt to the target CPU. More...

void	postDelayedFiq (uint32_t cpu)

void	copyGicState (GicV2Registers from, GicV2Registers to)
	GIC state transfer. More...

Tick	readDistributor (PacketPtr pkt)
	Handle a read to the distributor portion of the GIC. More...

uint32_t	readDistributor (ContextID ctx, Addr daddr, size_t resp_sz)

uint32_t	readDistributor (ContextID ctx, Addr daddr) override

Tick	readCpu (PacketPtr pkt)
	Handle a read to the cpu portion of the GIC. More...

uint32_t	readCpu (ContextID ctx, Addr daddr) override

Tick	writeDistributor (PacketPtr pkt)
	Handle a write to the distributor portion of the GIC. More...

void	writeDistributor (ContextID ctx, Addr daddr, uint32_t data, size_t data_sz)

void	writeDistributor (ContextID ctx, Addr daddr, uint32_t data) override

Tick	writeCpu (PacketPtr pkt)
	Handle a write to the cpu portion of the GIC. More...

void	writeCpu (ContextID ctx, Addr daddr, uint32_t data) override

Protected Member Functions inherited from gem5::BaseGic
virtual bool	blockIntUpdate () const
	When trasferring the state between two GICs (essentially writing architectural registers) an interrupt might be posted by the model. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
const uint32_t	gicdPIDR

const uint32_t	gicdIIDR

const uint32_t	giccIIDR

	sgi_id

Bitfield< 23, 16 >	cpu_list

Bitfield< 25, 24 >	list_type

	ack_id

Bitfield< 12, 10 >	cpu_id

Bitfield< 1 >	enableGrp1

Bitfield< 0 >	enableGrp0

EndBitUnion(CTLR) protected const AddrRange	cpuRange
	Address range for the distributor interface. More...

const AddrRangeList	addrRanges
	All address ranges used by this GIC. More...

const Tick	distPioDelay
	Latency for a distributor operation. More...

const Tick	cpuPioDelay
	Latency for a cpu operation. More...

const Tick	intLatency
	Latency for a interrupt to get to CPU. More...

bool	enabled
	Gic enabled. More...

const bool	haveGem5Extensions
	Are gem5 extensions available? More...

bool	gem5ExtensionsEnabled
	gem5 many-core extension enabled by driver More...

uint32_t	itLines
	Number of itLines enabled. More...

std::vector< BankedRegs * >	bankedRegs

uint32_t	intEnabled [INT_BITS_MAX-1]
	GICD_I{S,C}ENABLER{1..31} interrupt enable bits for global interrupts 1b per interrupt, 32 bits per word, 31 words. More...

uint32_t	pendingInt [INT_BITS_MAX-1]
	GICD_I{S,C}PENDR{1..31} interrupt pending bits for global interrupts 1b per interrupt, 32 bits per word, 31 words. More...

uint32_t	activeInt [INT_BITS_MAX-1]
	GICD_I{S,C}ACTIVER{1..31} interrupt active bits for global interrupts 1b per interrupt, 32 bits per word, 31 words. More...

uint32_t	intGroup [INT_BITS_MAX-1]
	GICD_IGROUPR{1..31} interrupt group bits for global interrupts 1b per interrupt, 32 bits per word, 31 words. More...

uint32_t	iccrpr [CPU_MAX]
	read only running priority register, 1 per cpu More...

uint8_t	intPriority [GLOBAL_INT_LINES]
	GICD_IPRIORITYR{8..255} an 8 bit priority (lower is higher priority) for each of the global (not replicated per CPU) interrupts. More...

uint32_t	intConfig [INT_BITS_MAX *2 - 2]
	GICD_ICFGR{2...63} 2 bit per interrupt signaling if it's level or edge sensitive and if it is 1:N or N:N. More...

uint8_t	cpuTarget [GLOBAL_INT_LINES]
	GICD_ITARGETSR{8..255} an 8 bit cpu target id for each global interrupt. More...

CTLR	cpuControl [CPU_MAX]
	GICC_CTLR: CPU interface control register. More...

uint8_t	cpuPriority [CPU_MAX]
	CPU priority. More...

uint8_t	cpuBpr [CPU_MAX]
	Binary point registers. More...

uint32_t	cpuHighestInt [CPU_MAX]
	highest interrupt that is interrupting CPU More...

uint64_t	cpuSgiPending [SGI_MAX]
	One bit per cpu per software interrupt that is pending for each possible sgi source. More...

uint64_t	cpuSgiActive [SGI_MAX]

uint32_t	cpuSgiPendingExt [CPU_MAX]
	SGI pending arrays for gem5 GIC extension mode, which instead keeps 16 SGI pending bits for each of the (large number of) CPUs. More...

uint32_t	cpuSgiActiveExt [CPU_MAX]

uint32_t	cpuPpiPending [CPU_MAX]
	One bit per private peripheral interrupt. More...

uint32_t	cpuPpiActive [CPU_MAX]

EventFunctionWrapper *	postIntEvent [CPU_MAX]

EventFunctionWrapper *	postFiqEvent [CPU_MAX]

int	pendingDelayedInterrupts

Protected Attributes inherited from gem5::BaseGic
Platform *	platform
	Platform this GIC belongs to. More...

Protected Attributes inherited from gem5::PioDevice
System *	sys

PioPort< PioDevice >	pioPort
	The pioPort that handles the requests for us and provides us requests that it sees. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Static Protected Attributes
static const AddrRange	GICD_IGROUPR

static const AddrRange	GICD_ISENABLER

static const AddrRange	GICD_ICENABLER

static const AddrRange	GICD_ISPENDR

static const AddrRange	GICD_ICPENDR

static const AddrRange	GICD_ISACTIVER

static const AddrRange	GICD_ICACTIVER

static const AddrRange	GICD_IPRIORITYR

static const AddrRange	GICD_ITARGETSR

static const AddrRange	GICD_ICFGR

static const int	SGI_MAX = 16

static const int	PPI_MAX = 16

static const int	SGI_MASK = 0xFFFF0000
	Mask off SGI's when setting/clearing pending bits. More...

static const int	NN_CONFIG_MASK = 0x55555555
	Mask for bits that config N:N mode in GICD_ICFGR's. More...

static const int	CPU_MAX = 256

static const int	SPURIOUS_INT = 1023

static const int	INT_BITS_MAX = 32

static const int	INT_LINES_MAX = 1020

static const int	GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX

static const int	GICC_BPR_MINIMUM = 2
	minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); chosen for consistency with Linux's in-kernel KVM GIC model More...

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Protected Member Functions inherited from gem5::GicV2Registers
static void	copyDistRegister (GicV2Registers from, GicV2Registers to, ContextID ctx, Addr daddr)

static void	copyCpuRegister (GicV2Registers from, GicV2Registers to, ContextID ctx, Addr daddr)

static void	copyBankedDistRange (System sys, GicV2Registers from, GicV2Registers *to, Addr daddr, size_t size)

static void	clearBankedDistRange (System sys, GicV2Registers to, Addr daddr, size_t size)

static void	copyDistRange (GicV2Registers from, GicV2Registers to, Addr daddr, size_t size)

static void	clearDistRange (GicV2Registers *to, Addr daddr, size_t size)

Detailed Description

Definition at line 91 of file gic_v2.hh.

Member Typedef Documentation

◆ Params

using gem5::GicV2::Params = GicV2Params

Definition at line 512 of file gic_v2.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum

protected

Enumerator
GICD_CTLR
GICD_TYPER
GICD_IIDR
GICD_SGIR
GICD_PIDR0
GICD_PIDR1
GICD_PIDR2
GICD_PIDR3
DIST_SIZE

Definition at line 95 of file gic_v2.hh.

◆ anonymous enum

anonymous enum

protected

Enumerator
GICC_CTLR
GICC_PMR
GICC_BPR
GICC_IAR
GICC_EOIR
GICC_RPR
GICC_HPPIR
GICC_ABPR
GICC_APR0
GICC_APR1
GICC_APR2
GICC_APR3
GICC_IIDR
GICC_DIR

Definition at line 125 of file gic_v2.hh.

Constructor & Destructor Documentation

◆ GicV2()

gem5::GicV2::GicV2 ( const Params & p )

Definition at line 122 of file gic_v2.cc.

References CPU_MAX, cpuBpr, cpuControl, cpuEnabled(), cpuHighestInt, cpuPriority, DPRINTF, gem5ExtensionsEnabled, GICC_BPR_MINIMUM, iccrpr, postDelayedFiq(), postDelayedInt(), postFiqEvent, postIntEvent, SPURIOUS_INT, and gem5::VegaISA::x.

◆ ~GicV2()

gem5::GicV2::~GicV2 ( )

Definition at line 161 of file gic_v2.cc.

References CPU_MAX, postFiqEvent, postIntEvent, and gem5::VegaISA::x.

Member Function Documentation

◆ BitUnion32()

gem5::GicV2::BitUnion32 ( SWI )

protected

◆ clearInt() [1/2]

void gem5::GicV2::clearInt	(	ContextID	ctx,
		uint32_t	int_num
	)

protected

Clears a cpu IRQ or FIQ signal.

Definition at line 981 of file gic_v2.cc.

References gem5::ArmISA::INT_FIQ, gem5::ArmISA::INT_IRQ, isFiq(), gem5::PioDevice::sys, and gem5::System::threads.

Referenced by readCpu(), and updateIntState().

◆ clearInt() [2/2]

void gem5::GicV2::clearInt ( uint32_t num )

overridevirtual

Clear an interrupt from a device that is connected to the GIC.

Depending on the configuration, the GIC may de-assert it's CPU line.

Parameters

num	number of interrupt to send

Implements gem5::BaseGic.

Definition at line 947 of file gic_v2.cc.

References DPRINTF, getCpuTarget(), getPendingInt(), intNumToBit(), intNumToWord(), isLevelSensitive(), and updateIntState().

◆ clearPPInt()

void gem5::GicV2::clearPPInt	(	uint32_t	num,
		uint32_t	cpu
	)

overridevirtual

Implements gem5::BaseGic.

Definition at line 966 of file gic_v2.cc.

References cpuPpiPending, DPRINTF, intNumToWord(), isLevelSensitive(), SGI_MAX, and updateIntState().

◆ copyGicState()

void gem5::GicV2::copyGicState	(	GicV2Registers *	from,
		GicV2Registers *	to
	)

protected

GIC state transfer.

CPU state (GICC_*)

Distributor state (GICD_*)

Definition at line 1056 of file gic_v2.cc.

References gem5::GicV2Registers::clearBankedDistRange(), gem5::GicV2Registers::clearDistRange(), gem5::GicV2Registers::copyBankedDistRange(), gem5::GicV2Registers::copyCpuRegister(), gem5::GicV2Registers::copyDistRange(), gem5::GicV2Registers::copyDistRegister(), GICC_BPR, GICC_CTLR, GICC_PMR, GICD_CTLR, GICD_ICACTIVER, GICD_ICENABLER, GICD_ICFGR, GICD_ICPENDR, GICD_IPRIORITYR, GICD_ISACTIVER, GICD_ISENABLER, GICD_ISPENDR, GICD_ITARGETSR, itLines, gem5::ArmISA::set, gem5::System::Threads::size(), gem5::AddrRange::start(), gem5::PioDevice::sys, gem5::System::threads, and gem5::PowerISA::to.

◆ cpuEnabled()

bool gem5::GicV2::cpuEnabled ( ContextID ctx ) const

inlineprotected

CPU enabled: Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set.

Definition at line 433 of file gic_v2.hh.

References cpuControl.

Referenced by GicV2(), readCpu(), softInt(), updateIntState(), updateRunPri(), and writeCpu().

◆ drain()

DrainState gem5::GicV2::drain ( )

overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 1038 of file gic_v2.cc.

References gem5::Drained, gem5::Draining, and pendingDelayedInterrupts.

◆ drainResume()

void gem5::GicV2::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 1049 of file gic_v2.cc.

References updateIntState().

◆ EndBitUnion() [1/2]

gem5::GicV2::EndBitUnion ( IAR )

protected

◆ EndBitUnion() [2/2]

gem5::GicV2::EndBitUnion ( SWI )

protected

◆ genSwiMask()

uint64_t gem5::GicV2::genSwiMask ( int cpu )

protected

generate a bit mask to check cpuSgi for an interrupt.

Definition at line 776 of file gic_v2.cc.

References panic_if, gem5::System::Threads::size(), gem5::PioDevice::sys, and gem5::System::threads.

Referenced by updateIntState(), and updateRunPri().

◆ getActiveInt()

uint32_t& gem5::GicV2::getActiveInt	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Definition at line 287 of file gic_v2.hh.

References gem5::GicV2::BankedRegs::activeInt, activeInt, getBankedRegs(), and INT_BITS_MAX.

Referenced by readCpu(), readDistributor(), updateIntState(), updateRunPri(), writeCpu(), and writeDistributor().

◆ getAddrRanges()

AddrRangeList gem5::GicV2::getAddrRanges ( ) const

inlineoverridevirtual

Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to.

Returns: a list of non-overlapping address ranges

Implements gem5::PioDevice.

Definition at line 523 of file gic_v2.hh.

References addrRanges.

◆ getBankedRegs()

GicV2::BankedRegs & gem5::GicV2::getBankedRegs ( ContextID ctx )

protected

Definition at line 696 of file gic_v2.cc.

References bankedRegs.

Referenced by getActiveInt(), getIntConfig(), getIntEnabled(), getIntGroup(), getIntPriority(), getPendingInt(), and unserialize().

◆ getCpuPriority()

uint8_t gem5::GicV2::getCpuPriority ( unsigned cpu )

protected

Definition at line 783 of file gic_v2.cc.

References cpuBpr, and cpuPriority.

Referenced by updateIntState().

◆ getCpuTarget()

uint8_t gem5::GicV2::getCpuTarget	(	ContextID	ctx,
		uint32_t	ix
	)		const

inlineprotected

Definition at line 363 of file gic_v2.hh.

References cpuTarget, fatal_if, gem5ExtensionsEnabled, INT_LINES_MAX, gem5::Named::name(), PPI_MAX, and SGI_MAX.

Referenced by clearInt(), readDistributor(), sendInt(), and updateIntState().

◆ getIntConfig()

uint32_t& gem5::GicV2::getIntConfig	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Reads the GICD_ICFGRn register.

Parameters

ctx	context id (PE specific)
ix	interrupt word index

Returns: the interrupt config word

SGIs and PPIs

Definition at line 346 of file gic_v2.hh.

References getBankedRegs(), INT_BITS_MAX, gem5::GicV2::BankedRegs::intConfig, and intConfig.

Referenced by isLevelSensitive(), readDistributor(), and writeDistributor().

◆ getIntEnabled()

uint32_t& gem5::GicV2::getIntEnabled	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Definition at line 256 of file gic_v2.hh.

References getBankedRegs(), gem5::GicV2::BankedRegs::intEnabled, and intEnabled.

Referenced by readDistributor(), updateIntState(), and writeDistributor().

◆ getIntGroup()

uint32_t& gem5::GicV2::getIntGroup	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Definition at line 303 of file gic_v2.hh.

References getBankedRegs(), INT_BITS_MAX, gem5::GicV2::BankedRegs::intGroup, and intGroup.

Referenced by isGroup0(), readDistributor(), and writeDistributor().

◆ getIntPriority()

uint8_t& gem5::GicV2::getIntPriority	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Definition at line 323 of file gic_v2.hh.

References getBankedRegs(), INT_LINES_MAX, intPriority, gem5::GicV2::BankedRegs::intPriority, PPI_MAX, and SGI_MAX.

Referenced by readDistributor(), updateIntState(), updateRunPri(), and writeDistributor().

◆ getPendingInt()

uint32_t& gem5::GicV2::getPendingInt	(	ContextID	ctx,
		uint32_t	ix
	)

inlineprotected

Definition at line 271 of file gic_v2.hh.

References getBankedRegs(), INT_BITS_MAX, gem5::GicV2::BankedRegs::pendingInt, and pendingInt.

Referenced by clearInt(), readCpu(), readDistributor(), sendInt(), updateIntState(), and writeDistributor().

◆ intNumToBit()

int gem5::GicV2::intNumToBit ( int num ) const

inlineprotected

Definition at line 490 of file gic_v2.hh.

Referenced by clearInt(), isGroup0(), isLevelSensitive(), readCpu(), sendInt(), updateIntState(), updateRunPri(), and writeCpu().

◆ intNumToWord()

int gem5::GicV2::intNumToWord ( int num ) const

inlineprotected

Definition at line 489 of file gic_v2.hh.

Referenced by clearInt(), clearPPInt(), isGroup0(), isLevelSensitive(), readCpu(), sendInt(), sendPPInt(), updateIntState(), updateRunPri(), and writeCpu().

◆ isFiq()

bool gem5::GicV2::isFiq	(	ContextID	ctx,
		uint32_t	int_num
	)

inlineprotected

This method checks if an interrupt ID must be signaled or has been signaled as a FIQ to the cpu.

It does that by reading:

1) GICD_IGROUPR: controls if the interrupt is part of group0 or group1. Only group0 interrupts can be signaled as FIQs.

2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal

Definition at line 417 of file gic_v2.hh.

References cpuControl, and isGroup0().

Referenced by clearInt(), and updateIntState().

◆ isGroup0()

bool gem5::GicV2::isGroup0	(	ContextID	ctx,
		uint32_t	int_num
	)

inlineprotected

Definition at line 400 of file gic_v2.hh.

References gem5::bits(), getIntGroup(), intNumToBit(), and intNumToWord().

Referenced by isFiq().

◆ isLevelSensitive()

bool gem5::GicV2::isLevelSensitive	(	ContextID	ctx,
		uint32_t	int_num
	)

inlineprotected

Definition at line 388 of file gic_v2.hh.

References gem5::bits(), getIntConfig(), intNumToBit(), intNumToWord(), and SPURIOUS_INT.

Referenced by clearInt(), clearPPInt(), readCpu(), and updateIntState().

◆ postDelayedFiq()

void gem5::GicV2::postDelayedFiq ( uint32_t cpu )

protected

Definition at line 1027 of file gic_v2.cc.

References gem5::ArmISA::INT_FIQ, pendingDelayedInterrupts, gem5::Drainable::signalDrainDone(), gem5::PioDevice::sys, and gem5::System::threads.

Referenced by GicV2().

◆ postDelayedInt()

void gem5::GicV2::postDelayedInt ( uint32_t cpu )

protected

Deliver a delayed interrupt to the target CPU.

Definition at line 1001 of file gic_v2.cc.

References gem5::ArmISA::INT_IRQ, pendingDelayedInterrupts, gem5::Drainable::signalDrainDone(), gem5::PioDevice::sys, and gem5::System::threads.

Referenced by GicV2().

◆ postFiq()

void gem5::GicV2::postFiq	(	uint32_t	cpu,
		Tick	when
	)

protected

Definition at line 1012 of file gic_v2.cc.

References gem5::EventManager::eventq, pendingDelayedInterrupts, postFiqEvent, and gem5::EventQueue::schedule().

Referenced by updateIntState().

◆ postInt()

void gem5::GicV2::postInt	(	uint32_t	cpu,
		Tick	when
	)

protected

Post an interrupt to a CPU with a delay.

Definition at line 992 of file gic_v2.cc.

References gem5::EventManager::eventq, pendingDelayedInterrupts, postIntEvent, and gem5::EventQueue::schedule().

Referenced by updateIntState().

◆ read()

Tick gem5::GicV2::read ( PacketPtr pkt )

overridevirtual

A PIO read to the device, immediately split up into readDistributor() or readCpu()

Implements gem5::PioDevice.

Definition at line 170 of file gic_v2.cc.

References gem5::X86ISA::addr, gem5::AddrRange::contains(), cpuRange, gem5::Packet::getAddr(), panic, readCpu(), and readDistributor().

◆ readCpu() [1/2]

uint32_t gem5::GicV2::readCpu	(	ContextID	ctx,
		Addr	daddr
	)

overrideprotectedvirtual

Implements gem5::GicV2Registers.

Definition at line 362 of file gic_v2.cc.

References gem5::bits(), clearInt(), cpuBpr, cpuControl, cpuEnabled(), cpuHighestInt, cpuPpiActive, cpuPpiPending, cpuPriority, cpuSgiActive, cpuSgiActiveExt, cpuSgiPending, cpuSgiPendingExt, DPRINTF, enabled, gem5ExtensionsEnabled, getActiveInt(), getPendingInt(), GICC_BPR, GICC_CTLR, GICC_HPPIR, GICC_IAR, GICC_IIDR, GICC_PMR, GICC_RPR, giccIIDR, iccrpr, intNumToBit(), intNumToWord(), isLevelSensitive(), gem5::System::Threads::numRunning(), panic, panic_if, PPI_MAX, SGI_MAX, SPURIOUS_INT, gem5::PioDevice::sys, gem5::System::threads, updateIntState(), updateRunPri(), and gem5::VegaISA::x.

◆ readCpu() [2/2]

Tick gem5::GicV2::readCpu ( PacketPtr pkt )

protected

Handle a read to the cpu portion of the GIC.

Parameters

pkt	packet to respond to

Definition at line 345 of file gic_v2.cc.

References cpuPioDelay, cpuRange, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::makeAtomicResponse(), gem5::Packet::req, gem5::Packet::setLE(), and gem5::AddrRange::start().

Referenced by read().

◆ readDistributor() [1/3]

uint32_t gem5::GicV2::readDistributor	(	ContextID	ctx,
		Addr	daddr
	)

inlineoverrideprotectedvirtual

Implements gem5::GicV2Registers.

Definition at line 554 of file gic_v2.hh.

References readDistributor().

◆ readDistributor() [2/3]

uint32_t gem5::GicV2::readDistributor	(	ContextID	ctx,
		Addr	daddr,
		size_t	resp_sz
	)

protected

◆ readDistributor() [3/3]

Tick gem5::GicV2::readDistributor ( PacketPtr pkt )

protected

Handle a read to the distributor portion of the GIC.

Parameters

pkt	packet to respond to

Definition at line 197 of file gic_v2.cc.

References distPioDelay, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getSize(), gem5::Packet::makeAtomicResponse(), panic, gem5::Packet::req, and gem5::Packet::setLE().

Referenced by read(), and readDistributor().

◆ sendInt()

void gem5::GicV2::sendInt ( uint32_t num )

overridevirtual

Post an interrupt from a device that is connected to the GIC.

Depending on the configuration, the GIC will pass this interrupt on through to a CPU.

Parameters

num	number of interrupt to send

Implements gem5::BaseGic.

Definition at line 924 of file gic_v2.cc.

References DPRINTF, gem5ExtensionsEnabled, getCpuTarget(), getPendingInt(), intNumToBit(), intNumToWord(), panic, panic_if, PPI_MAX, SGI_MAX, and updateIntState().

◆ sendPPInt()

void gem5::GicV2::sendPPInt	(	uint32_t	num,
		uint32_t	cpu
	)

overridevirtual

Interface call for private peripheral interrupts.

Parameters

num	number of interrupt to send
cpu	CPU to forward interrupt to

Implements gem5::BaseGic.

Definition at line 938 of file gic_v2.cc.

References cpuPpiPending, DPRINTF, intNumToWord(), SGI_MAX, and updateIntState().

◆ serialize()

void gem5::GicV2::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 1128 of file gic_v2.cc.

References activeInt, bankedRegs, CPU_MAX, cpuBpr, cpuControl, cpuHighestInt, cpuPpiActive, cpuPpiPending, cpuPriority, cpuSgiActive, cpuSgiActiveExt, cpuSgiPending, cpuSgiPendingExt, cpuTarget, gem5::csprintf(), DPRINTF, enabled, gem5ExtensionsEnabled, GLOBAL_INT_LINES, gem5::ArmISA::i, iccrpr, INT_BITS_MAX, intConfig, intEnabled, intGroup, intPriority, itLines, pendingInt, SERIALIZE_ARRAY, SERIALIZE_SCALAR, and SGI_MAX.

◆ softInt()

void gem5::GicV2::softInt	(	ContextID	ctx,
		SWI	swi
	)

protected

software generated interrupt

Parameters

data	data to decode that indicates which cpus to interrupt

Definition at line 706 of file gic_v2.cc.

References cpu_list, cpuEnabled(), cpuSgiPending, cpuSgiPendingExt, DPRINTF, gem5ExtensionsEnabled, gem5::ArmISA::i, gem5::System::Threads::size(), gem5::PioDevice::sys, gem5::System::threads, updateIntState(), and gem5::VegaISA::x.

Referenced by writeDistributor().

◆ supportsVersion()

bool gem5::GicV2::supportsVersion ( GicVersion version )

overridevirtual

Check if version supported.

Implements gem5::BaseGic.

Definition at line 1021 of file gic_v2.cc.

References gem5::BaseGic::GIC_V2.

◆ unserialize()

void gem5::GicV2::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 1173 of file gic_v2.cc.

References activeInt, CPU_MAX, cpuBpr, cpuControl, cpuHighestInt, cpuPpiActive, cpuPpiPending, cpuPriority, cpuSgiActive, cpuSgiActiveExt, cpuSgiPending, cpuSgiPendingExt, cpuTarget, gem5::csprintf(), gem5::Serializable::currentSection(), DPRINTF, enabled, gem5::CheckpointIn::entryExists(), gem5ExtensionsEnabled, getBankedRegs(), GLOBAL_INT_LINES, gem5::ArmISA::i, iccrpr, INT_BITS_MAX, intConfig, intEnabled, intGroup, intPriority, itLines, pendingInt, postIntEvent, gem5::EventManager::schedule(), gem5::CheckpointIn::sectionExists(), SGI_MAX, gem5::GicV2::BankedRegs::unserialize(), UNSERIALIZE_ARRAY, UNSERIALIZE_OPT_SCALAR, and UNSERIALIZE_SCALAR.

◆ updateIntState()

void gem5::GicV2::updateIntState ( int hint )

protected

See if some processor interrupt flags need to be enabled/disabled.

Parameters

hint	which set of interrupts needs to be checked

Definition at line 794 of file gic_v2.cc.

References gem5::bits(), gem5::BaseGic::blockIntUpdate(), clearInt(), cpuEnabled(), cpuHighestInt, cpuPpiPending, cpuSgiPending, cpuSgiPendingExt, gem5::curTick(), DPRINTF, enabled, gem5ExtensionsEnabled, genSwiMask(), getActiveInt(), getCpuPriority(), getCpuTarget(), getIntEnabled(), getIntPriority(), getPendingInt(), INT_BITS_MAX, intLatency, intNumToBit(), intNumToWord(), isFiq(), isLevelSensitive(), itLines, gem5::System::Threads::numRunning(), postFiq(), postInt(), PPI_MAX, SGI_MAX, gem5::System::Threads::size(), SPURIOUS_INT, gem5::PioDevice::sys, gem5::System::threads, and gem5::VegaISA::x.

Referenced by clearInt(), clearPPInt(), drainResume(), readCpu(), sendInt(), sendPPInt(), softInt(), writeCpu(), and writeDistributor().

◆ updateRunPri()

void gem5::GicV2::updateRunPri ( )

protected

Update the register that records priority of the highest priority active interrupt.

Definition at line 895 of file gic_v2.cc.

References cpuEnabled(), cpuPpiActive, cpuSgiActive, cpuSgiActiveExt, genSwiMask(), getActiveInt(), getIntPriority(), gem5::ArmISA::i, iccrpr, intNumToBit(), intNumToWord(), itLines, PPI_MAX, SGI_MAX, gem5::System::Threads::size(), gem5::PioDevice::sys, and gem5::System::threads.

Referenced by readCpu(), writeCpu(), and writeDistributor().

◆ write()

Tick gem5::GicV2::write ( PacketPtr pkt )

overridevirtual

A PIO read to the device, immediately split up into writeDistributor() or writeCpu()

Implements gem5::PioDevice.

Definition at line 184 of file gic_v2.cc.

References gem5::X86ISA::addr, gem5::AddrRange::contains(), cpuRange, gem5::Packet::getAddr(), panic, writeCpu(), and writeDistributor().

◆ writeCpu() [1/2]

void gem5::GicV2::writeCpu	(	ContextID	ctx,
		Addr	daddr,
		uint32_t	data
	)

overrideprotectedvirtual

Implements gem5::GicV2Registers.

Definition at line 633 of file gic_v2.cc.

References cpuBpr, cpuControl, cpuEnabled(), cpuPpiActive, cpuPriority, cpuSgiActive, cpuSgiActiveExt, data, DPRINTF, gem5ExtensionsEnabled, getActiveInt(), GICC_APR0, GICC_APR1, GICC_APR2, GICC_APR3, GICC_BPR, GICC_BPR_MINIMUM, GICC_CTLR, GICC_DIR, GICC_EOIR, GICC_PMR, intNumToBit(), intNumToWord(), panic, PPI_MAX, SGI_MAX, updateIntState(), updateRunPri(), and warn.

◆ writeCpu() [2/2]

Tick gem5::GicV2::writeCpu ( PacketPtr pkt )

protected

Handle a write to the cpu portion of the GIC.

Parameters

pkt	packet to respond to

Definition at line 615 of file gic_v2.cc.

References cpuPioDelay, cpuRange, data, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getLE(), gem5::Packet::makeAtomicResponse(), gem5::Packet::req, and gem5::AddrRange::start().

Referenced by write().

◆ writeDistributor() [1/3]

void gem5::GicV2::writeDistributor	(	ContextID	ctx,
		Addr	daddr,
		uint32_t	data
	)

inlineoverrideprotectedvirtual

Implements gem5::GicV2Registers.

Definition at line 572 of file gic_v2.hh.

References data, and writeDistributor().

◆ writeDistributor() [2/3]

void gem5::GicV2::writeDistributor	(	ContextID	ctx,
		Addr	daddr,
		uint32_t	data,
		size_t	data_sz
	)

protected

◆ writeDistributor() [3/3]

Tick gem5::GicV2::writeDistributor ( PacketPtr pkt )

protected

Handle a write to the distributor portion of the GIC.

Parameters

pkt	packet to respond to

Definition at line 444 of file gic_v2.cc.

References distPioDelay, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getLE(), gem5::Packet::getSize(), gem5::Packet::makeAtomicResponse(), panic, and gem5::Packet::req.

Referenced by write(), and writeDistributor().

Member Data Documentation

◆ ack_id

gem5::GicV2::ack_id

protected

Definition at line 169 of file gic_v2.hh.

◆ activeInt

uint32_t gem5::GicV2::activeInt[INT_BITS_MAX-1]

protected

GICD_I{S,C}ACTIVER{1..31} interrupt active bits for global interrupts 1b per interrupt, 32 bits per word, 31 words.

Definition at line 284 of file gic_v2.hh.

Referenced by getActiveInt(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ addrRanges

const AddrRangeList gem5::GicV2::addrRanges

protected

All address ranges used by this GIC.

Definition at line 187 of file gic_v2.hh.

Referenced by getAddrRanges().

◆ bankedRegs

std::vector<BankedRegs*> gem5::GicV2::bankedRegs

protected

Definition at line 246 of file gic_v2.hh.

Referenced by getBankedRegs(), and serialize().

◆ cpu_id

Bitfield<12,10> gem5::GicV2::cpu_id

protected

Definition at line 170 of file gic_v2.hh.

◆ cpu_list

Bitfield<23,16> gem5::GicV2::cpu_list

protected

Definition at line 164 of file gic_v2.hh.

Referenced by softInt().

◆ CPU_MAX

const int gem5::GicV2::CPU_MAX = 256

staticprotected

Definition at line 152 of file gic_v2.hh.

Referenced by GicV2(), serialize(), unserialize(), and ~GicV2().

◆ cpuBpr

uint8_t gem5::GicV2::cpuBpr[CPU_MAX]

protected

Binary point registers.

Definition at line 449 of file gic_v2.hh.

Referenced by getCpuPriority(), GicV2(), readCpu(), serialize(), unserialize(), and writeCpu().

◆ cpuControl

CTLR gem5::GicV2::cpuControl[CPU_MAX]

protected

GICC_CTLR: CPU interface control register.

Definition at line 442 of file gic_v2.hh.

Referenced by cpuEnabled(), GicV2(), isFiq(), readCpu(), serialize(), unserialize(), and writeCpu().

◆ cpuHighestInt

uint32_t gem5::GicV2::cpuHighestInt[CPU_MAX]

protected

highest interrupt that is interrupting CPU

Definition at line 452 of file gic_v2.hh.

Referenced by GicV2(), readCpu(), serialize(), unserialize(), and updateIntState().

◆ cpuPioDelay

const Tick gem5::GicV2::cpuPioDelay

protected

Latency for a cpu operation.

Definition at line 193 of file gic_v2.hh.

Referenced by readCpu(), and writeCpu().

◆ cpuPpiActive

uint32_t gem5::GicV2::cpuPpiActive[CPU_MAX]

protected

Definition at line 470 of file gic_v2.hh.

Referenced by readCpu(), serialize(), unserialize(), updateRunPri(), and writeCpu().

◆ cpuPpiPending

uint32_t gem5::GicV2::cpuPpiPending[CPU_MAX]

protected

One bit per private peripheral interrupt.

Only upper 16 bits will be used since PPI interrupts are numberred from 16 to 32

Definition at line 469 of file gic_v2.hh.

Referenced by clearPPInt(), readCpu(), sendPPInt(), serialize(), unserialize(), and updateIntState().

◆ cpuPriority

uint8_t gem5::GicV2::cpuPriority[CPU_MAX]

protected

CPU priority.

Definition at line 445 of file gic_v2.hh.

Referenced by getCpuPriority(), GicV2(), readCpu(), serialize(), unserialize(), and writeCpu().

◆ cpuRange

EndBitUnion (CTLR) protected const AddrRange gem5::GicV2::cpuRange

protected

Address range for the distributor interface.

Address range for the CPU interfaces

Definition at line 184 of file gic_v2.hh.

Referenced by read(), readCpu(), write(), and writeCpu().

◆ cpuSgiActive

uint64_t gem5::GicV2::cpuSgiActive[SGI_MAX]

protected

Definition at line 459 of file gic_v2.hh.

Referenced by readCpu(), serialize(), unserialize(), updateRunPri(), and writeCpu().

◆ cpuSgiActiveExt

uint32_t gem5::GicV2::cpuSgiActiveExt[CPU_MAX]

protected

Definition at line 465 of file gic_v2.hh.

Referenced by readCpu(), serialize(), unserialize(), updateRunPri(), and writeCpu().

◆ cpuSgiPending

uint64_t gem5::GicV2::cpuSgiPending[SGI_MAX]

protected

One bit per cpu per software interrupt that is pending for each possible sgi source.

Indexed by SGI number. Each byte in generating cpu id and bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt for CPU 2.

Definition at line 458 of file gic_v2.hh.

Referenced by readCpu(), serialize(), softInt(), unserialize(), and updateIntState().

◆ cpuSgiPendingExt

uint32_t gem5::GicV2::cpuSgiPendingExt[CPU_MAX]

protected

SGI pending arrays for gem5 GIC extension mode, which instead keeps 16 SGI pending bits for each of the (large number of) CPUs.

Definition at line 464 of file gic_v2.hh.

Referenced by readCpu(), serialize(), softInt(), unserialize(), and updateIntState().

◆ cpuTarget

uint8_t gem5::GicV2::cpuTarget[GLOBAL_INT_LINES]

protected

GICD_ITARGETSR{8..255} an 8 bit cpu target id for each global interrupt.

Definition at line 360 of file gic_v2.hh.

Referenced by getCpuTarget(), serialize(), unserialize(), and writeDistributor().

◆ distPioDelay

const Tick gem5::GicV2::distPioDelay

protected

Latency for a distributor operation.

Definition at line 190 of file gic_v2.hh.

Referenced by readDistributor(), and writeDistributor().

◆ enabled

bool gem5::GicV2::enabled

protected

Gic enabled.

Definition at line 200 of file gic_v2.hh.

Referenced by readCpu(), readDistributor(), serialize(), unserialize(), updateIntState(), and writeDistributor().

◆ enableGrp0

Bitfield<0> gem5::GicV2::enableGrp0

protected

Definition at line 176 of file gic_v2.hh.

◆ enableGrp1

Bitfield<1> gem5::GicV2::enableGrp1

protected

Definition at line 175 of file gic_v2.hh.

◆ gem5ExtensionsEnabled

bool gem5::GicV2::gem5ExtensionsEnabled

protected

gem5 many-core extension enabled by driver

Definition at line 206 of file gic_v2.hh.

Referenced by getCpuTarget(), GicV2(), readCpu(), sendInt(), serialize(), softInt(), unserialize(), updateIntState(), writeCpu(), and writeDistributor().

◆ GICC_BPR_MINIMUM

const int gem5::GicV2::GICC_BPR_MINIMUM = 2

staticprotected

minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); chosen for consistency with Linux's in-kernel KVM GIC model

Definition at line 160 of file gic_v2.hh.

Referenced by GicV2(), and writeCpu().

◆ giccIIDR

const uint32_t gem5::GicV2::giccIIDR

protected

Definition at line 111 of file gic_v2.hh.

Referenced by readCpu().

◆ GICD_ICACTIVER

const AddrRange gem5::GicV2::GICD_ICACTIVER

staticprotected

Definition at line 119 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ICENABLER

const AddrRange gem5::GicV2::GICD_ICENABLER

staticprotected

Definition at line 115 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ICFGR

const AddrRange gem5::GicV2::GICD_ICFGR

staticprotected

Definition at line 122 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ICPENDR

const AddrRange gem5::GicV2::GICD_ICPENDR

staticprotected

Definition at line 117 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_IGROUPR

const AddrRange gem5::GicV2::GICD_IGROUPR

staticprotected

Definition at line 113 of file gic_v2.hh.

Referenced by readDistributor(), and writeDistributor().

◆ GICD_IPRIORITYR

const AddrRange gem5::GicV2::GICD_IPRIORITYR

staticprotected

Definition at line 120 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ISACTIVER

const AddrRange gem5::GicV2::GICD_ISACTIVER

staticprotected

Definition at line 118 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ISENABLER

const AddrRange gem5::GicV2::GICD_ISENABLER

staticprotected

Definition at line 114 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ISPENDR

const AddrRange gem5::GicV2::GICD_ISPENDR

staticprotected

Definition at line 116 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ GICD_ITARGETSR

const AddrRange gem5::GicV2::GICD_ITARGETSR

staticprotected

Definition at line 121 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), and writeDistributor().

◆ gicdIIDR

const uint32_t gem5::GicV2::gicdIIDR

protected

Definition at line 110 of file gic_v2.hh.

Referenced by readDistributor().

◆ gicdPIDR

const uint32_t gem5::GicV2::gicdPIDR

protected

Definition at line 109 of file gic_v2.hh.

Referenced by readDistributor().

◆ GLOBAL_INT_LINES

const int gem5::GicV2::GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX

staticprotected

Definition at line 156 of file gic_v2.hh.

Referenced by serialize(), and unserialize().

◆ haveGem5Extensions

const bool gem5::GicV2::haveGem5Extensions

protected

Are gem5 extensions available?

Definition at line 203 of file gic_v2.hh.

Referenced by readDistributor(), and writeDistributor().

◆ iccrpr

uint32_t gem5::GicV2::iccrpr[CPU_MAX]

protected

read only running priority register, 1 per cpu

Definition at line 314 of file gic_v2.hh.

Referenced by GicV2(), readCpu(), serialize(), unserialize(), and updateRunPri().

◆ INT_BITS_MAX

const int gem5::GicV2::INT_BITS_MAX = 32

staticprotected

Definition at line 154 of file gic_v2.hh.

Referenced by getActiveInt(), getIntConfig(), getIntGroup(), getPendingInt(), readDistributor(), serialize(), unserialize(), and updateIntState().

◆ INT_LINES_MAX

const int gem5::GicV2::INT_LINES_MAX = 1020

staticprotected

Definition at line 155 of file gic_v2.hh.

Referenced by getCpuTarget(), getIntPriority(), and readDistributor().

◆ intConfig

uint32_t gem5::GicV2::intConfig[INT_BITS_MAX *2 - 2]

protected

GICD_ICFGR{2...63} 2 bit per interrupt signaling if it's level or edge sensitive and if it is 1:N or N:N.

Definition at line 337 of file gic_v2.hh.

Referenced by getIntConfig(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ intEnabled

uint32_t gem5::GicV2::intEnabled[INT_BITS_MAX-1]

protected

GICD_I{S,C}ENABLER{1..31} interrupt enable bits for global interrupts 1b per interrupt, 32 bits per word, 31 words.

Definition at line 253 of file gic_v2.hh.

Referenced by getIntEnabled(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ intGroup

uint32_t gem5::GicV2::intGroup[INT_BITS_MAX-1]

protected

GICD_IGROUPR{1..31} interrupt group bits for global interrupts 1b per interrupt, 32 bits per word, 31 words.

Definition at line 300 of file gic_v2.hh.

Referenced by getIntGroup(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ intLatency

const Tick gem5::GicV2::intLatency

protected

Latency for a interrupt to get to CPU.

Definition at line 196 of file gic_v2.hh.

Referenced by updateIntState().

◆ intPriority

uint8_t gem5::GicV2::intPriority[GLOBAL_INT_LINES]

protected

GICD_IPRIORITYR{8..255} an 8 bit priority (lower is higher priority) for each of the global (not replicated per CPU) interrupts.

Definition at line 320 of file gic_v2.hh.

Referenced by getIntPriority(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ itLines

uint32_t gem5::GicV2::itLines

protected

Number of itLines enabled.

Definition at line 209 of file gic_v2.hh.

Referenced by copyGicState(), readDistributor(), serialize(), unserialize(), updateIntState(), and updateRunPri().

◆ list_type

Bitfield<25,24> gem5::GicV2::list_type

protected

Definition at line 165 of file gic_v2.hh.

◆ NN_CONFIG_MASK

const int gem5::GicV2::NN_CONFIG_MASK = 0x55555555

staticprotected

Mask for bits that config N:N mode in GICD_ICFGR's.

Definition at line 150 of file gic_v2.hh.

Referenced by writeDistributor().

◆ pendingDelayedInterrupts

int gem5::GicV2::pendingDelayedInterrupts

protected

Definition at line 509 of file gic_v2.hh.

Referenced by drain(), postDelayedFiq(), postDelayedInt(), postFiq(), and postInt().

◆ pendingInt

uint32_t gem5::GicV2::pendingInt[INT_BITS_MAX-1]

protected

GICD_I{S,C}PENDR{1..31} interrupt pending bits for global interrupts 1b per interrupt, 32 bits per word, 31 words.

Definition at line 268 of file gic_v2.hh.

Referenced by getPendingInt(), serialize(), gem5::GicV2::BankedRegs::unserialize(), and unserialize().

◆ postFiqEvent

EventFunctionWrapper* gem5::GicV2::postFiqEvent[CPU_MAX]

protected

Definition at line 508 of file gic_v2.hh.

Referenced by GicV2(), postFiq(), and ~GicV2().

◆ postIntEvent

EventFunctionWrapper* gem5::GicV2::postIntEvent[CPU_MAX]

protected

Definition at line 507 of file gic_v2.hh.

Referenced by GicV2(), postInt(), unserialize(), and ~GicV2().

◆ PPI_MAX

const int gem5::GicV2::PPI_MAX = 16

staticprotected

Definition at line 144 of file gic_v2.hh.

Referenced by getCpuTarget(), getIntPriority(), readCpu(), sendInt(), gem5::GicV2::BankedRegs::serialize(), gem5::GicV2::BankedRegs::unserialize(), updateIntState(), updateRunPri(), writeCpu(), and writeDistributor().

◆ sgi_id

gem5::GicV2::sgi_id

protected

Definition at line 163 of file gic_v2.hh.

◆ SGI_MASK

const int gem5::GicV2::SGI_MASK = 0xFFFF0000

staticprotected

Mask off SGI's when setting/clearing pending bits.

Definition at line 147 of file gic_v2.hh.

Referenced by writeDistributor().

◆ SGI_MAX

const int gem5::GicV2::SGI_MAX = 16

staticprotected

Definition at line 143 of file gic_v2.hh.

Referenced by clearPPInt(), getCpuTarget(), getIntPriority(), readCpu(), sendInt(), sendPPInt(), gem5::GicV2::BankedRegs::serialize(), serialize(), gem5::GicV2::BankedRegs::unserialize(), unserialize(), updateIntState(), updateRunPri(), writeCpu(), and writeDistributor().

◆ SPURIOUS_INT

const int gem5::GicV2::SPURIOUS_INT = 1023

staticprotected

Definition at line 153 of file gic_v2.hh.

Referenced by GicV2(), isLevelSensitive(), readCpu(), and updateIntState().

The documentation for this class was generated from the following files:

dev/arm/gic_v2.hh
dev/arm/gic_v2.cc

Classes

Public Types

Public Member Functions

Protected Types

Protected Member Functions

Protected Attributes

Static Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Member Enumeration Documentation

◆ anonymous enum

◆ anonymous enum

Constructor & Destructor Documentation

◆ GicV2()

◆ ~GicV2()

Member Function Documentation

◆ BitUnion32()

◆ clearInt() [1/2]

◆ clearInt() [2/2]

◆ clearPPInt()

◆ copyGicState()

◆ cpuEnabled()

◆ drain()

◆ drainResume()

◆ EndBitUnion() [1/2]

◆ EndBitUnion() [2/2]

◆ genSwiMask()

◆ getActiveInt()

◆ getAddrRanges()

◆ getBankedRegs()

◆ getCpuPriority()

◆ getCpuTarget()

◆ getIntConfig()

◆ getIntEnabled()

◆ getIntGroup()

◆ getIntPriority()

◆ getPendingInt()

◆ intNumToBit()

◆ intNumToWord()

◆ isFiq()

◆ isGroup0()

◆ isLevelSensitive()

◆ postDelayedFiq()

◆ postDelayedInt()

◆ postFiq()

◆ postInt()

◆ read()

◆ readCpu() [1/2]

◆ readCpu() [2/2]

◆ readDistributor() [1/3]

◆ readDistributor() [2/3]

◆ readDistributor() [3/3]

◆ sendInt()

◆ sendPPInt()

◆ serialize()

◆ softInt()

◆ supportsVersion()

◆ unserialize()

◆ updateIntState()

◆ updateRunPri()

◆ write()

◆ writeCpu() [1/2]

◆ writeCpu() [2/2]

◆ writeDistributor() [1/3]

◆ writeDistributor() [2/3]

◆ writeDistributor() [3/3]

Member Data Documentation

◆ ack_id

◆ activeInt

◆ addrRanges

◆ bankedRegs

◆ cpu_id

◆ cpu_list

◆ CPU_MAX

◆ cpuBpr

◆ cpuControl

◆ cpuHighestInt

◆ cpuPioDelay