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gem5
v22.1.0.0
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#include <hsa_queue.hh>
Public Attributes | |
| _hsa_queue_t | hsa_queue |
| uint32_t | reserved1 [4] |
| volatile uint64_t | write_dispatch_id |
| uint32_t | group_segment_aperture_base_hi |
| uint32_t | private_segment_aperture_base_hi |
| uint32_t | max_cu_id |
| uint32_t | max_wave_id |
| volatile uint64_t | max_legacy_doorbell_dispatch_id_plus_1 |
| volatile uint32_t | legacy_doorbell_lock |
| uint32_t | reserved2 [9] |
| volatile uint64_t | read_dispatch_id |
| uint32_t | read_dispatch_id_field_base_byte_offset |
| uint32_t | compute_tmpring_size_waves: 12 |
| uint32_t | compute_tmpring_size_wavesize: 13 |
| uint32_t | compute_tmpring_size_pad: 7 |
| uint32_t | scratch_resource_descriptor [4] |
| uint64_t | scratch_backing_memory_location |
| uint64_t | scratch_backing_memory_byte_size |
| uint32_t | scratch_workitem_byte_size |
| _amd_queue_properties32_t | queue_properties |
| uint32_t | reserved3 [2] |
| _hsa_signal_t | queue_inactive_signal |
| uint32_t | reserved4 [14] |
Definition at line 64 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::compute_tmpring_size_pad |
Definition at line 80 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::compute_tmpring_size_waves |
Definition at line 78 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::compute_tmpring_size_wavesize |
Definition at line 79 of file hsa_queue.hh.
Referenced by gem5::Wavefront::initRegState(), and gem5::GPUCommandProcessor::MQDDmaEvent().
| uint32_t gem5::_amd_queue_t::group_segment_aperture_base_hi |
Definition at line 69 of file hsa_queue.hh.
| _hsa_queue_t gem5::_amd_queue_t::hsa_queue |
Definition at line 66 of file hsa_queue.hh.
| volatile uint32_t gem5::_amd_queue_t::legacy_doorbell_lock |
Definition at line 74 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::max_cu_id |
Definition at line 71 of file hsa_queue.hh.
| volatile uint64_t gem5::_amd_queue_t::max_legacy_doorbell_dispatch_id_plus_1 |
Definition at line 73 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::max_wave_id |
Definition at line 72 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::private_segment_aperture_base_hi |
Definition at line 70 of file hsa_queue.hh.
| _hsa_signal_t gem5::_amd_queue_t::queue_inactive_signal |
Definition at line 87 of file hsa_queue.hh.
Referenced by gem5::GPUCommandProcessor::MQDDmaEvent(), and gem5::GPUCommandProcessor::WaitScratchDmaEvent().
| _amd_queue_properties32_t gem5::_amd_queue_t::queue_properties |
Definition at line 85 of file hsa_queue.hh.
| volatile uint64_t gem5::_amd_queue_t::read_dispatch_id |
Definition at line 76 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::read_dispatch_id_field_base_byte_offset |
Definition at line 77 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::reserved1[4] |
Definition at line 67 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::reserved2[9] |
Definition at line 75 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::reserved3[2] |
Definition at line 86 of file hsa_queue.hh.
| uint32_t gem5::_amd_queue_t::reserved4[14] |
Definition at line 88 of file hsa_queue.hh.
| uint64_t gem5::_amd_queue_t::scratch_backing_memory_byte_size |
Definition at line 83 of file hsa_queue.hh.
| uint64_t gem5::_amd_queue_t::scratch_backing_memory_location |
Definition at line 82 of file hsa_queue.hh.
Referenced by gem5::Wavefront::initRegState().
| uint32_t gem5::_amd_queue_t::scratch_resource_descriptor[4] |
Definition at line 81 of file hsa_queue.hh.
Referenced by gem5::Wavefront::initRegState().
| uint32_t gem5::_amd_queue_t::scratch_workitem_byte_size |
Definition at line 84 of file hsa_queue.hh.
Referenced by gem5::Wavefront::initRegState().
| volatile uint64_t gem5::_amd_queue_t::write_dispatch_id |
Definition at line 68 of file hsa_queue.hh.