gem5  v22.0.0.1
hsa_queue.hh
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31 
32 #ifndef __DEV_HSA_HSA_QUEUE_HH__
33 #define __DEV_HSA_HSA_QUEUE_HH__
34 
35 #include <cstdint>
36 
37 namespace gem5
38 {
39 
41 {
44 };
45 
47 {
48  uint64_t handle;
49 };
50 
52 {
54  uint32_t features;
55  void *base_address;
57  uint32_t size;
58  uint32_t reserved1;
59  uint64_t id;
60 };
61 
62 typedef uint32_t _amd_queue_properties32_t;
63 
65 {
67  uint32_t reserved1[4];
68  volatile uint64_t write_dispatch_id;
71  uint32_t max_cu_id;
72  uint32_t max_wave_id;
74  volatile uint32_t legacy_doorbell_lock;
75  uint32_t reserved2[9];
76  volatile uint64_t read_dispatch_id;
86  uint32_t reserved3[2];
88  uint32_t reserved4[14];
89 };
90 
91 } // namespace gem5
92 
93 #endif // __DEV_HSA_HSA_QUEUE_HH__
gem5::_amd_queue_t
Definition: hsa_queue.hh:64
gem5::_amd_queue_t::compute_tmpring_size_waves
uint32_t compute_tmpring_size_waves
Definition: hsa_queue.hh:78
gem5::_amd_queue_t::max_wave_id
uint32_t max_wave_id
Definition: hsa_queue.hh:72
gem5::_hsa_queue_t::id
uint64_t id
Definition: hsa_queue.hh:59
gem5::_amd_queue_t::queue_properties
_amd_queue_properties32_t queue_properties
Definition: hsa_queue.hh:85
gem5::_HSA_QUEUE_TYPE_SINGLE
@ _HSA_QUEUE_TYPE_SINGLE
Definition: hsa_queue.hh:43
gem5::_hsa_signal_t
Definition: hsa_queue.hh:46
gem5::_HSA_QUEUE_TYPE_MULTI
@ _HSA_QUEUE_TYPE_MULTI
Definition: hsa_queue.hh:42
gem5::_amd_queue_t::scratch_backing_memory_byte_size
uint64_t scratch_backing_memory_byte_size
Definition: hsa_queue.hh:83
gem5::_amd_queue_t::group_segment_aperture_base_hi
uint32_t group_segment_aperture_base_hi
Definition: hsa_queue.hh:69
gem5::_amd_queue_t::reserved4
uint32_t reserved4[14]
Definition: hsa_queue.hh:88
gem5::_amd_queue_t::read_dispatch_id
volatile uint64_t read_dispatch_id
Definition: hsa_queue.hh:76
gem5::_amd_queue_t::reserved3
uint32_t reserved3[2]
Definition: hsa_queue.hh:86
gem5::_hsa_queue_type_t
_hsa_queue_type_t
Definition: hsa_queue.hh:40
gem5::_hsa_queue_t::size
uint32_t size
Definition: hsa_queue.hh:57
gem5::_amd_queue_t::legacy_doorbell_lock
volatile uint32_t legacy_doorbell_lock
Definition: hsa_queue.hh:74
gem5::_amd_queue_t::scratch_workitem_byte_size
uint32_t scratch_workitem_byte_size
Definition: hsa_queue.hh:84
gem5::_amd_queue_t::scratch_resource_descriptor
uint32_t scratch_resource_descriptor[4]
Definition: hsa_queue.hh:81
gem5::_amd_queue_t::private_segment_aperture_base_hi
uint32_t private_segment_aperture_base_hi
Definition: hsa_queue.hh:70
gem5::_amd_queue_t::write_dispatch_id
volatile uint64_t write_dispatch_id
Definition: hsa_queue.hh:68
gem5::_amd_queue_t::max_legacy_doorbell_dispatch_id_plus_1
volatile uint64_t max_legacy_doorbell_dispatch_id_plus_1
Definition: hsa_queue.hh:73
gem5::_hsa_queue_t::reserved1
uint32_t reserved1
Definition: hsa_queue.hh:58
gem5::_hsa_queue_t::type
_hsa_queue_type_t type
Definition: hsa_queue.hh:53
gem5::_hsa_signal_t::handle
uint64_t handle
Definition: hsa_queue.hh:48
gem5::_amd_queue_t::compute_tmpring_size_pad
uint32_t compute_tmpring_size_pad
Definition: hsa_queue.hh:80
gem5::_hsa_queue_t::doorbell_signal
_hsa_signal_t doorbell_signal
Definition: hsa_queue.hh:56
gem5::_amd_queue_properties32_t
uint32_t _amd_queue_properties32_t
Definition: hsa_queue.hh:62
gem5::_amd_queue_t::reserved2
uint32_t reserved2[9]
Definition: hsa_queue.hh:75
gem5::_amd_queue_t::read_dispatch_id_field_base_byte_offset
uint32_t read_dispatch_id_field_base_byte_offset
Definition: hsa_queue.hh:77
gem5::_amd_queue_t::queue_inactive_signal
_hsa_signal_t queue_inactive_signal
Definition: hsa_queue.hh:87
gem5::_amd_queue_t::scratch_backing_memory_location
uint64_t scratch_backing_memory_location
Definition: hsa_queue.hh:82
gem5::_amd_queue_t::compute_tmpring_size_wavesize
uint32_t compute_tmpring_size_wavesize
Definition: hsa_queue.hh:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::_amd_queue_t::hsa_queue
_hsa_queue_t hsa_queue
Definition: hsa_queue.hh:66
gem5::_hsa_queue_t
Definition: hsa_queue.hh:51
gem5::_amd_queue_t::max_cu_id
uint32_t max_cu_id
Definition: hsa_queue.hh:71
gem5::_hsa_queue_t::features
uint32_t features
Definition: hsa_queue.hh:54
gem5::_amd_queue_t::reserved1
uint32_t reserved1[4]
Definition: hsa_queue.hh:67
gem5::_hsa_queue_t::base_address
void * base_address
Definition: hsa_queue.hh:55

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