gem5  v21.1.0.2
gpu_command_processor.hh
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33 
45 #ifndef __DEV_HSA_GPU_COMMAND_PROCESSOR_HH__
46 #define __DEV_HSA_GPU_COMMAND_PROCESSOR_HH__
47 
48 #include <cstdint>
49 #include <functional>
50 
51 #include "base/logging.hh"
52 #include "base/trace.hh"
53 #include "base/types.hh"
54 #include "debug/GPUCommandProc.hh"
55 #include "dev/dma_virt_device.hh"
57 #include "dev/hsa/hsa_signal.hh"
61 #include "params/GPUCommandProcessor.hh"
62 
63 namespace gem5
64 {
65 
66 struct GPUCommandProcessorParams;
67 class GPUComputeDriver;
68 class GPUDispatcher;
69 class Shader;
70 
72 {
73  public:
74  typedef GPUCommandProcessorParams Params;
75  typedef std::function<void(const uint64_t &)> HsaSignalCallbackFunction;
76 
77  GPUCommandProcessor() = delete;
79 
81 
82  void setShader(Shader *shader);
83  Shader* shader();
85 
86  enum AgentCmd
87  {
88  Nop = 0,
89  Steal = 1
90  };
91 
92  void submitAgentDispatchPkt(void *raw_pkt, uint32_t queue_id,
93  Addr host_pkt_addr);
94  void submitDispatchPkt(void *raw_pkt, uint32_t queue_id,
95  Addr host_pkt_addr);
96  void submitVendorPkt(void *raw_pkt, uint32_t queue_id,
97  Addr host_pkt_addr);
99 
100  void dispatchPkt(HSAQueueEntry *task);
101  void signalWakeupEvent(uint32_t event_id);
102 
103  Tick write(PacketPtr pkt) override { return 0; }
104  Tick read(PacketPtr pkt) override { return 0; }
105  AddrRangeList getAddrRanges() const override;
106  System *system();
107 
108  void updateHsaSignal(Addr signal_handle, uint64_t signal_value,
109  HsaSignalCallbackFunction function =
110  [] (const uint64_t &) { });
111 
112  uint64_t functionalReadHsaSignal(Addr signal_handle);
113 
115  {
116  return signal_handle + offsetof(amd_signal_t, value);
117  }
118 
120  {
121  return signal_handle + offsetof(amd_signal_t, event_mailbox_ptr);
122  }
123 
125  {
126  return signal_handle + offsetof(amd_signal_t, event_id);
127  }
128 
129  private:
133 
134  // Typedefing dmaRead and dmaWrite function pointer
135  typedef void (DmaDevice::*DmaFnPtr)(Addr, int, Event*, uint8_t*, Tick);
136  void initABI(HSAQueueEntry *task);
138  void translateOrDie(Addr vaddr, Addr &paddr) override;
139 
152  void
154  const uint32_t &readDispIdOffset)
155  {
164  task->queueId())->hostReadIndexPtr - readDispIdOffset;
165 
170  auto *mqdDmaEvent = new DmaVirtCallback<int>(
171  [ = ] (const int &) { MQDDmaEvent(task); });
172 
174  sizeof(_amd_queue_t), mqdDmaEvent, &task->amdQueue);
175  }
176 
184  void
186  {
199  if (task->privMemPerItem() >
201  // TODO: Raising this signal will potentially nuke scratch
202  // space for in-flight kernels that were launched from this
203  // queue. We need to drain all kernels and deschedule the
204  // queue before raising this signal. For now, just assert if
205  // there are any in-flight kernels and tell the user that this
206  // feature still needs to be implemented.
207  fatal_if(hsaPP->inFlightPkts(task->queueId()) > 1,
208  "Needed more scratch, but kernels are in flight for "
209  "this queue and it is unsafe to reallocate scratch. "
210  "We need to implement additional intelligence in the "
211  "hardware scheduling logic to support CP-driven "
212  "queue draining and scheduling.");
213  DPRINTF(GPUCommandProc, "Not enough scratch space to launch "
214  "kernel (%x available, %x requested bytes per "
215  "workitem). Asking host runtime to allocate more "
216  "space.\n",
218  task->privMemPerItem());
219 
221  [ = ] (const uint64_t &dma_buffer)
222  { WaitScratchDmaEvent(task, dma_buffer); });
223 
224  } else {
225  DPRINTF(GPUCommandProc, "Sufficient scratch space, launching "
226  "kernel (%x available, %x requested bytes per "
227  "workitem).\n",
229  task->privMemPerItem());
230  dispatchPkt(task);
231  }
232  }
233 
238  void
239  WaitScratchDmaEvent(HSAQueueEntry *task, const uint64_t &dmaBuffer)
240  {
241  if (dmaBuffer == 0) {
242  DPRINTF(GPUCommandProc, "Host scratch allocation complete. "
243  "Attempting to re-read MQD\n");
252  auto cb = new DmaVirtCallback<int>(
253  [ = ] (const int &) { MQDDmaEvent(task); });
254 
255  dmaReadVirt(task->hostAMDQueueAddr, sizeof(_amd_queue_t), cb,
256  &task->amdQueue);
257  } else {
262  Addr value_addr = getHsaSignalValueAddr(
264  DPRINTF(GPUCommandProc, "Polling queue inactive signal at "
265  "%p.\n", value_addr);
266  auto cb = new DmaVirtCallback<uint64_t>(
267  [ = ] (const uint64_t &dma_buffer)
268  { WaitScratchDmaEvent(task, dma_buffer); } );
269  dmaReadVirt(value_addr, sizeof(Addr), cb, &cb->dmaBuffer);
270  }
271  }
272 };
273 
274 } // namespace gem5
275 
276 #endif // __DEV_HSA_GPU_COMMAND_PROCESSOR_HH__
gem5::_amd_queue_t
Definition: hsa_queue.hh:66
gem5::GPUCommandProcessor::Params
GPUCommandProcessorParams Params
Definition: gpu_command_processor.hh:74
gem5::GPUCommandProcessor::getHsaSignalEventAddr
Addr getHsaSignalEventAddr(Addr signal_handle)
Definition: gpu_command_processor.hh:124
hsa_queue_entry.hh
gem5::GPUCommandProcessor::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gpu_command_processor.hh:104
gem5::GPUCommandProcessor::shader
Shader * shader()
Definition: gpu_command_processor.cc:366
gem5::GPUCommandProcessor::hsaPP
HSAPacketProcessor * hsaPP
Definition: gpu_command_processor.hh:137
gem5::SparcISA::Nop
Nop class.
Definition: nop.hh:48
gem5::HSAQueueEntry::privMemPerItem
int privMemPerItem() const
Definition: hsa_queue_entry.hh:196
gem5::GPUCommandProcessor::signalWakeupEvent
void signalWakeupEvent(uint32_t event_id)
Definition: gpu_command_processor.cc:321
gem5::GPUCommandProcessor::attachDriver
void attachDriver(GPUComputeDriver *driver)
Definition: gpu_command_processor.cc:221
gem5::HSAQueueDescriptor::hostReadIndexPtr
uint64_t hostReadIndexPtr
Definition: hsa_packet_processor.hh:84
gem5::DmaVirtDevice::DmaVirtCallback
Wraps a std::function object in a DmaCallback.
Definition: dma_virt_device.hh:55
gem5::DmaVirtDevice::dmaReadVirt
void dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0)
Initiate a DMA read from virtual address host_addr.
Definition: dma_virt_device.cc:45
hsa_packet_processor.hh
gem5::GPUCommandProcessor::DmaFnPtr
void(DmaDevice::* DmaFnPtr)(Addr, int, Event *, uint8_t *, Tick)
Definition: gpu_command_processor.hh:135
gem5::HSAQueueEntry
Definition: hsa_queue_entry.hh:61
gem5::HSAPacketProcessor::getQueueDesc
HSAQueueDescriptor * getQueueDesc(uint32_t queId)
Definition: hsa_packet_processor.hh:298
gem5::HSAQueueEntry::queueId
uint32_t queueId() const
Definition: hsa_queue_entry.hh:149
gem5::GPUCommandProcessor::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: gpu_command_processor.cc:353
gem5::GPUCommandProcessor::GPUCommandProcessor
GPUCommandProcessor()=delete
gem5::HSAPacketProcessor::inFlightPkts
uint64_t inFlightPkts(uint32_t queId)
Definition: hsa_packet_processor.hh:309
gem5::GPUCommandProcessor::WaitScratchDmaEvent
void WaitScratchDmaEvent(HSAQueueEntry *task, const uint64_t &dmaBuffer)
Poll on queue_inactive signal until the runtime can get around to taking care of our lack of scratch ...
Definition: gpu_command_processor.hh:239
gem5::GPUCommandProcessor::hsaPacketProc
HSAPacketProcessor & hsaPacketProc()
Definition: gpu_command_processor.cc:60
gem5::GPUCommandProcessor::getHsaSignalMailboxAddr
Addr getHsaSignalMailboxAddr(Addr signal_handle)
Definition: gpu_command_processor.hh:119
gem5::GPUCommandProcessor::submitDispatchPkt
void submitDispatchPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
submitDispatchPkt() is the entry point into the CP from the HSAPP and is only meant to be used with A...
Definition: gpu_command_processor.cc:98
gem5::GPUCommandProcessor::updateHsaSignal
void updateHsaSignal(Addr signal_handle, uint64_t signal_value, HsaSignalCallbackFunction function=[](const uint64_t &) { })
Definition: gpu_command_processor.cc:186
gem5::GPUCommandProcessor::MQDDmaEvent
void MQDDmaEvent(HSAQueueEntry *task)
Perform a DMA read of the MQD that corresponds to a hardware queue descriptor (HQD).
Definition: gpu_command_processor.hh:185
gem5::HSAQueueEntry::amdQueue
_amd_queue_t amdQueue
Keep a copy of the AMD HSA queue because we need info from some of its fields to initialize register ...
Definition: hsa_queue_entry.hh:309
gem5::GPUCommandProcessor::AgentCmd
AgentCmd
Definition: gpu_command_processor.hh:86
gem5::System
Definition: system.hh:77
gem5::GPUCommandProcessor
Definition: gpu_command_processor.hh:71
gem5::GPUCommandProcessor::dispatchPkt
void dispatchPkt(HSAQueueEntry *task)
Once the CP has finished extracting all relevant information about a task and has initialized the ABI...
Definition: gpu_command_processor.cc:315
gem5::GPUCommandProcessor::setShader
void setShader(Shader *shader)
Definition: gpu_command_processor.cc:360
gem5::HSAPacketProcessor
Definition: hsa_packet_processor.hh:224
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::GPUCommandProcessor::_driver
GPUComputeDriver * _driver
Definition: gpu_command_processor.hh:132
gem5::DmaDevice
Definition: dma_device.hh:203
gem5::GPUCommandProcessor::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: gpu_command_processor.hh:103
gem5::GPUCommandProcessor::submitAgentDispatchPkt
void submitAgentDispatchPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
submitAgentDispatchPkt() is for accepting agent dispatch packets.
Definition: gpu_command_processor.cc:268
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::GPUCommandProcessor::getHsaSignalValueAddr
Addr getHsaSignalValueAddr(Addr signal_handle)
Definition: gpu_command_processor.hh:114
gem5::HSAQueueEntry::hostAMDQueueAddr
Addr hostAMDQueueAddr
Host-side addr of the amd_queue_t on which this task was queued.
Definition: hsa_queue_entry.hh:302
hsa_signal.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GPUCommandProcessor::system
System * system()
Definition: gpu_command_processor.cc:347
gem5::_hsa_signal_t::handle
uint64_t handle
Definition: hsa_queue.hh:50
gem5::GPUCommandProcessor::_shader
Shader * _shader
Definition: gpu_command_processor.hh:130
types.hh
gem5::GPUCommandProcessor::ReadDispIdOffsetDmaEvent
void ReadDispIdOffsetDmaEvent(HSAQueueEntry *task, const uint32_t &readDispIdOffset)
Perform a DMA read of the read_dispatch_id_field_base_byte_offset field, which follows directly after...
Definition: gpu_command_processor.hh:153
gem5::GPUCommandProcessor::submitVendorPkt
void submitVendorPkt(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr)
submitVendorPkt() is for accepting vendor-specific packets from the HSAPP.
Definition: gpu_command_processor.cc:254
gem5::GPUCommandProcessor::functionalReadHsaSignal
uint64_t functionalReadHsaSignal(Addr signal_handle)
Definition: gpu_command_processor.cc:177
gem5::GPUComputeDriver
Definition: gpu_compute_driver.hh:64
logging.hh
dma_virt_device.hh
trace.hh
gem5::GPUDispatcher
Definition: dispatcher.hh:64
dispatcher.hh
gem5::DmaVirtDevice
Definition: dma_virt_device.hh:42
gpu_compute_driver.hh
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::GPUCommandProcessor::translateOrDie
void translateOrDie(Addr vaddr, Addr &paddr) override
Function used to translate from virtual to physical addresses.
Definition: gpu_command_processor.cc:66
gem5::_amd_queue_t::queue_inactive_signal
_hsa_signal_t queue_inactive_signal
Definition: hsa_queue.hh:89
std::list< AddrRange >
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5::_amd_queue_t::compute_tmpring_size_wavesize
uint32_t compute_tmpring_size_wavesize
Definition: hsa_queue.hh:81
gem5::amd_signal_s
Definition: hsa_signal.hh:52
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GPUCommandProcessor::dispatcher
GPUDispatcher & dispatcher
Definition: gpu_command_processor.hh:131
gem5::GPUCommandProcessor::Steal
@ Steal
Definition: gpu_command_processor.hh:89
gem5::GPUCommandProcessor::HsaSignalCallbackFunction
std::function< void(const uint64_t &)> HsaSignalCallbackFunction
Definition: gpu_command_processor.hh:75
gem5::GPUCommandProcessor::driver
GPUComputeDriver * driver()
Definition: gpu_command_processor.cc:231
gem5::Shader
Definition: shader.hh:84
gem5::GPUCommandProcessor::initABI
void initABI(HSAQueueEntry *task)
The CP is responsible for traversing all HSA-ABI-related data structures from memory and initializing...
Definition: gpu_command_processor.cc:333

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