gem5 v24.0.0.0
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timing_expr.hh
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1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * These classes define an expression language over uint64_t with only
40 * a few operators. This can be used to form expressions for the extra
41 * delay required in variable execution time instructions.
42 *
43 * Expressions, in evaluation, will have access to the ThreadContext and
44 * a StaticInst.
45 */
46
47#ifndef __CPU_TIMING_EXPR_HH__
48#define __CPU_TIMING_EXPR_HH__
49
50#include "cpu/static_inst.hh"
51#include "cpu/thread_context.hh"
52#include "enums/TimingExprOp.hh"
53#include "params/TimingExpr.hh"
54#include "params/TimingExprBin.hh"
55#include "params/TimingExprIf.hh"
56#include "params/TimingExprLet.hh"
57#include "params/TimingExprLiteral.hh"
58#include "params/TimingExprRef.hh"
59#include "params/TimingExprSrcReg.hh"
60#include "params/TimingExprUn.hh"
61#include "sim/sim_object.hh"
62
63namespace gem5
64{
65
69class TimingExprLet;
70
89
90class TimingExpr : public SimObject
91{
92 public:
93 TimingExpr(const TimingExprParams &params) :
95 { }
96
97 virtual uint64_t eval(TimingExprEvalContext &context) = 0;
98};
99
101{
102 public:
103 uint64_t value;
104
105 TimingExprLiteral(const TimingExprLiteralParams &params) :
108 { }
109
110 uint64_t eval(TimingExprEvalContext &context) { return value; }
111};
112
114{
115 public:
116 unsigned int index;
117
118 TimingExprSrcReg(const TimingExprSrcRegParams &params) :
121 { }
122
123 uint64_t eval(TimingExprEvalContext &context);
124};
125
127{
128 public:
131
132 TimingExprLet(const TimingExprLetParams &params) :
136 { }
137
138 uint64_t eval(TimingExprEvalContext &context);
139};
140
142{
143 public:
144 unsigned int index;
145
146 TimingExprRef(const TimingExprRefParams &params) :
149 { }
150
151 uint64_t eval(TimingExprEvalContext &context);
152};
153
155{
156 public:
157 enums::TimingExprOp op;
159
160 TimingExprUn(const TimingExprUnParams &params) :
162 op(params.op),
163 arg(params.arg)
164 { }
165
166 uint64_t eval(TimingExprEvalContext &context);
167};
168
170{
171 public:
172 enums::TimingExprOp op;
175
176 TimingExprBin(const TimingExprBinParams &params) :
178 op(params.op),
181 { }
182
183 uint64_t eval(TimingExprEvalContext &context);
184};
185
187{
188 public:
192
193 TimingExprIf(const TimingExprIfParams &params) :
198 { }
199
200 uint64_t eval(TimingExprEvalContext &context);
201};
202
203} // namespace gem5
204
205#endif
Abstract superclass for simulation objects.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
uint64_t eval(TimingExprEvalContext &context)
enums::TimingExprOp op
TimingExprBin(const TimingExprBinParams &params)
Object to gather the visible context for evaluation.
TimingExprLet * let
Context visible as sub expressions.
std::vector< uint64_t > results
std::vector< bool > resultAvailable
TimingExprEvalContext(const StaticInstPtr &inst_, ThreadContext *thread_, TimingExprLet *let_)
const StaticInstPtr & inst
Special visible context.
TimingExpr * trueExpr
uint64_t eval(TimingExprEvalContext &context)
TimingExprIf(const TimingExprIfParams &params)
TimingExpr * falseExpr
TimingExpr * cond
TimingExprLet(const TimingExprLetParams &params)
std::vector< TimingExpr * > defns
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
TimingExprLiteral(const TimingExprLiteralParams &params)
TimingExprRef(const TimingExprRefParams &params)
uint64_t eval(TimingExprEvalContext &context)
TimingExprSrcReg(const TimingExprSrcRegParams &params)
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
enums::TimingExprOp op
TimingExprUn(const TimingExprUnParams &params)
virtual uint64_t eval(TimingExprEvalContext &context)=0
TimingExpr(const TimingExprParams &params)
STL vector class.
Definition stl.hh:37
const Params & params() const
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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