gem5  v22.0.0.2
timing_expr.cc
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37 
38 #include "cpu/timing_expr.hh"
39 
40 #include "base/intmath.hh"
41 
42 namespace gem5
43 {
44 
46  ThreadContext *thread_, TimingExprLet *let_) :
47  inst(inst_), thread(thread_), let(let_)
48 {
49  /* Reserve space to hold the results of evaluating the
50  * let expressions */
51  if (let) {
52  unsigned int num_defns = let->defns.size();
53 
54  results.resize(num_defns, 0);
55  resultAvailable.resize(num_defns, false);
56  }
57 }
58 
59 uint64_t
61 {
62  return context.inst->srcRegIdx(index).index();
63 }
64 
65 uint64_t
67 {
68  return context.thread->readIntReg(reg->eval(context));
69 }
70 
71 uint64_t
73 {
74  TimingExprEvalContext new_context(context.inst, context.thread, this);
75 
76  return expr->eval(new_context);
77 }
78 
79 uint64_t
81 {
82  /* Lookup the result, evaluating if necessary. @todo, this
83  * should have more error checking */
84  if (!context.resultAvailable[index]) {
85  context.results[index] = context.let->defns[index]->eval(context);
86  context.resultAvailable[index] = true;
87  }
88 
89  return context.results[index];
90 }
91 
92 uint64_t
94 {
95  uint64_t arg_value = arg->eval(context);
96  uint64_t ret = 0;
97 
98  switch (op) {
99  case enums::timingExprSizeInBits:
100  if (arg_value == 0)
101  ret = 0;
102  else
103  ret = ceilLog2(arg_value);
104  break;
105  case enums::timingExprNot:
106  ret = arg_value != 0;
107  break;
108  case enums::timingExprInvert:
109  ret = ~arg_value;
110  break;
111  case enums::timingExprSignExtend32To64:
112  ret = static_cast<int64_t>(
113  static_cast<int32_t>(arg_value));
114  break;
115  case enums::timingExprAbs:
116  if (static_cast<int64_t>(arg_value) < 0)
117  ret = -arg_value;
118  else
119  ret = arg_value;
120  break;
121  default:
122  break;
123  }
124 
125  return ret;
126 }
127 
128 uint64_t
130 {
131  uint64_t left_value = left->eval(context);
132  uint64_t right_value = right->eval(context);
133  uint64_t ret = 0;
134 
135  switch (op) {
136  case enums::timingExprAdd:
137  ret = left_value + right_value;
138  break;
139  case enums::timingExprSub:
140  ret = left_value - right_value;
141  break;
142  case enums::timingExprUMul:
143  ret = left_value * right_value;
144  break;
145  case enums::timingExprUDiv:
146  if (right_value != 0) {
147  ret = left_value / right_value;
148  }
149  break;
150  case enums::timingExprUCeilDiv:
151  if (right_value != 0) {
152  ret = (left_value + (right_value - 1)) / right_value;
153  }
154  break;
155  case enums::timingExprSMul:
156  ret = static_cast<int64_t>(left_value) *
157  static_cast<int64_t>(right_value);
158  break;
159  case enums::timingExprSDiv:
160  if (right_value != 0) {
161  ret = static_cast<int64_t>(left_value) /
162  static_cast<int64_t>(right_value);
163  }
164  break;
165  case enums::timingExprEqual:
166  ret = left_value == right_value;
167  break;
168  case enums::timingExprNotEqual:
169  ret = left_value != right_value;
170  break;
171  case enums::timingExprULessThan:
172  ret = left_value < right_value;
173  break;
174  case enums::timingExprUGreaterThan:
175  ret = left_value > right_value;
176  break;
177  case enums::timingExprSLessThan:
178  ret = static_cast<int64_t>(left_value) <
179  static_cast<int64_t>(right_value);
180  break;
181  case enums::timingExprSGreaterThan:
182  ret = static_cast<int64_t>(left_value) >
183  static_cast<int64_t>(right_value);
184  break;
185  case enums::timingExprAnd:
186  ret = (left_value != 0) && (right_value != 0);
187  break;
188  case enums::timingExprOr:
189  ret = (left_value != 0) || (right_value != 0);
190  break;
191  default:
192  break;
193  }
194 
195  return ret;
196 }
197 
198 uint64_t
200 {
201  uint64_t cond_value = cond->eval(context);
202 
203  if (cond_value != 0)
204  return trueExpr->eval(context);
205  else
206  return falseExpr->eval(context);
207 }
208 
209 } // namespace gem5
gem5::TimingExprLet
Definition: timing_expr.hh:140
gem5::TimingExprBin::left
TimingExpr * left
Definition: timing_expr.hh:187
gem5::TimingExprBin::op
enums::TimingExprOp op
Definition: timing_expr.hh:186
gem5::TimingExprLet::defns
std::vector< TimingExpr * > defns
Definition: timing_expr.hh:143
gem5::TimingExprUn::op
enums::TimingExprOp op
Definition: timing_expr.hh:171
gem5::TimingExprBin::right
TimingExpr * right
Definition: timing_expr.hh:188
gem5::TimingExprEvalContext::let
TimingExprLet * let
Context visible as sub expressions.
Definition: timing_expr.hh:83
timing_expr.hh
gem5::TimingExprEvalContext::inst
const StaticInstPtr & inst
Special visible context.
Definition: timing_expr.hh:77
gem5::TimingExprLet::expr
TimingExpr * expr
Definition: timing_expr.hh:144
gem5::RefCountingPtr< StaticInst >
gem5::TimingExprIf::trueExpr
TimingExpr * trueExpr
Definition: timing_expr.hh:204
gem5::TimingExpr::eval
virtual uint64_t eval(TimingExprEvalContext &context)=0
gem5::TimingExprUn::arg
TimingExpr * arg
Definition: timing_expr.hh:172
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::TimingExprLet::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:72
gem5::TimingExprRef::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:80
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:225
gem5::TimingExprEvalContext::results
std::vector< uint64_t > results
Definition: timing_expr.hh:84
gem5::TimingExprEvalContext::TimingExprEvalContext
TimingExprEvalContext(const StaticInstPtr &inst_, ThreadContext *thread_, TimingExprLet *let_)
Definition: timing_expr.cc:45
gem5::TimingExprEvalContext
Object to gather the visible context for evaluation.
Definition: timing_expr.hh:73
gem5::TimingExprEvalContext::resultAvailable
std::vector< bool > resultAvailable
Definition: timing_expr.hh:85
gem5::TimingExprSrcReg::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:60
gem5::TimingExprEvalContext::thread
ThreadContext * thread
Definition: timing_expr.hh:78
gem5::TimingExprReadIntReg::reg
TimingExpr * reg
Definition: timing_expr.hh:130
gem5::TimingExprRef::index
unsigned int index
Definition: timing_expr.hh:158
gem5::ceilLog2
static constexpr int ceilLog2(const T &n)
Definition: intmath.hh:84
gem5::TimingExprBin::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:129
gem5::TimingExprSrcReg::index
unsigned int index
Definition: timing_expr.hh:117
gem5::TimingExprIf::cond
TimingExpr * cond
Definition: timing_expr.hh:203
gem5::TimingExprReadIntReg::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:66
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::TimingExprIf::falseExpr
TimingExpr * falseExpr
Definition: timing_expr.hh:205
gem5::TimingExprUn::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:93
gem5::TimingExprIf::eval
uint64_t eval(TimingExprEvalContext &context)
Definition: timing_expr.cc:199

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