gem5 v24.0.0.0
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timing_expr.cc
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1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "cpu/timing_expr.hh"
39
40#include "base/intmath.hh"
41
42namespace gem5
43{
44
46 ThreadContext *thread_, TimingExprLet *let_) :
47 inst(inst_), thread(thread_), let(let_)
48{
49 /* Reserve space to hold the results of evaluating the
50 * let expressions */
51 if (let) {
52 unsigned int num_defns = let->defns.size();
53
54 results.resize(num_defns, 0);
55 resultAvailable.resize(num_defns, false);
56 }
57}
58
59uint64_t
61{
62 return context.thread->getReg(context.inst->srcRegIdx(index));
63}
64
65uint64_t
67{
68 TimingExprEvalContext new_context(context.inst, context.thread, this);
69
70 return expr->eval(new_context);
71}
72
73uint64_t
75{
76 /* Lookup the result, evaluating if necessary. @todo, this
77 * should have more error checking */
78 if (!context.resultAvailable[index]) {
79 context.results[index] = context.let->defns[index]->eval(context);
80 context.resultAvailable[index] = true;
81 }
82
83 return context.results[index];
84}
85
86uint64_t
88{
89 uint64_t arg_value = arg->eval(context);
90 uint64_t ret = 0;
91
92 switch (op) {
93 case enums::timingExprSizeInBits:
94 if (arg_value == 0)
95 ret = 0;
96 else
97 ret = ceilLog2(arg_value);
98 break;
99 case enums::timingExprNot:
100 ret = arg_value != 0;
101 break;
102 case enums::timingExprInvert:
103 ret = ~arg_value;
104 break;
105 case enums::timingExprSignExtend32To64:
106 ret = static_cast<int64_t>(
107 static_cast<int32_t>(arg_value));
108 break;
109 case enums::timingExprAbs:
110 if (static_cast<int64_t>(arg_value) < 0)
111 ret = -arg_value;
112 else
113 ret = arg_value;
114 break;
115 default:
116 break;
117 }
118
119 return ret;
120}
121
122uint64_t
124{
125 uint64_t left_value = left->eval(context);
126 uint64_t right_value = right->eval(context);
127 uint64_t ret = 0;
128
129 switch (op) {
130 case enums::timingExprAdd:
131 ret = left_value + right_value;
132 break;
133 case enums::timingExprSub:
134 ret = left_value - right_value;
135 break;
136 case enums::timingExprUMul:
137 ret = left_value * right_value;
138 break;
139 case enums::timingExprUDiv:
140 if (right_value != 0) {
141 ret = left_value / right_value;
142 }
143 break;
144 case enums::timingExprUCeilDiv:
145 if (right_value != 0) {
146 ret = (left_value + (right_value - 1)) / right_value;
147 }
148 break;
149 case enums::timingExprSMul:
150 ret = static_cast<int64_t>(left_value) *
151 static_cast<int64_t>(right_value);
152 break;
153 case enums::timingExprSDiv:
154 if (right_value != 0) {
155 ret = static_cast<int64_t>(left_value) /
156 static_cast<int64_t>(right_value);
157 }
158 break;
159 case enums::timingExprEqual:
160 ret = left_value == right_value;
161 break;
162 case enums::timingExprNotEqual:
163 ret = left_value != right_value;
164 break;
165 case enums::timingExprULessThan:
166 ret = left_value < right_value;
167 break;
168 case enums::timingExprUGreaterThan:
169 ret = left_value > right_value;
170 break;
171 case enums::timingExprSLessThan:
172 ret = static_cast<int64_t>(left_value) <
173 static_cast<int64_t>(right_value);
174 break;
175 case enums::timingExprSGreaterThan:
176 ret = static_cast<int64_t>(left_value) >
177 static_cast<int64_t>(right_value);
178 break;
179 case enums::timingExprAnd:
180 ret = (left_value != 0) && (right_value != 0);
181 break;
182 case enums::timingExprOr:
183 ret = (left_value != 0) || (right_value != 0);
184 break;
185 default:
186 break;
187 }
188
189 return ret;
190}
191
192uint64_t
194{
195 uint64_t cond_value = cond->eval(context);
196
197 if (cond_value != 0)
198 return trueExpr->eval(context);
199 else
200 return falseExpr->eval(context);
201}
202
203} // namespace gem5
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId &reg) const
uint64_t eval(TimingExprEvalContext &context)
enums::TimingExprOp op
Object to gather the visible context for evaluation.
TimingExprLet * let
Context visible as sub expressions.
std::vector< uint64_t > results
std::vector< bool > resultAvailable
TimingExprEvalContext(const StaticInstPtr &inst_, ThreadContext *thread_, TimingExprLet *let_)
const StaticInstPtr & inst
Special visible context.
TimingExpr * trueExpr
uint64_t eval(TimingExprEvalContext &context)
TimingExpr * falseExpr
TimingExpr * cond
std::vector< TimingExpr * > defns
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
enums::TimingExprOp op
virtual uint64_t eval(TimingExprEvalContext &context)=0
static constexpr int ceilLog2(const T &n)
Definition intmath.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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