47 inst(inst_), thread(thread_), let(let_)
52 unsigned int num_defns =
let->
defns.size();
89 uint64_t arg_value =
arg->
eval(context);
93 case enums::timingExprSizeInBits:
99 case enums::timingExprNot:
100 ret = arg_value != 0;
102 case enums::timingExprInvert:
105 case enums::timingExprSignExtend32To64:
106 ret =
static_cast<int64_t
>(
107 static_cast<int32_t
>(arg_value));
109 case enums::timingExprAbs:
110 if (
static_cast<int64_t
>(arg_value) < 0)
125 uint64_t left_value =
left->
eval(context);
126 uint64_t right_value =
right->
eval(context);
130 case enums::timingExprAdd:
131 ret = left_value + right_value;
133 case enums::timingExprSub:
134 ret = left_value - right_value;
136 case enums::timingExprUMul:
137 ret = left_value * right_value;
139 case enums::timingExprUDiv:
140 if (right_value != 0) {
141 ret = left_value / right_value;
144 case enums::timingExprUCeilDiv:
145 if (right_value != 0) {
146 ret = (left_value + (right_value - 1)) / right_value;
149 case enums::timingExprSMul:
150 ret =
static_cast<int64_t
>(left_value) *
151 static_cast<int64_t
>(right_value);
153 case enums::timingExprSDiv:
154 if (right_value != 0) {
155 ret =
static_cast<int64_t
>(left_value) /
156 static_cast<int64_t
>(right_value);
159 case enums::timingExprEqual:
160 ret = left_value == right_value;
162 case enums::timingExprNotEqual:
163 ret = left_value != right_value;
165 case enums::timingExprULessThan:
166 ret = left_value < right_value;
168 case enums::timingExprUGreaterThan:
169 ret = left_value > right_value;
171 case enums::timingExprSLessThan:
172 ret =
static_cast<int64_t
>(left_value) <
173 static_cast<int64_t
>(right_value);
175 case enums::timingExprSGreaterThan:
176 ret =
static_cast<int64_t
>(left_value) >
177 static_cast<int64_t
>(right_value);
179 case enums::timingExprAnd:
180 ret = (left_value != 0) && (right_value != 0);
182 case enums::timingExprOr:
183 ret = (left_value != 0) || (right_value != 0);
195 uint64_t cond_value =
cond->
eval(context);
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId ®) const
uint64_t eval(TimingExprEvalContext &context)
Object to gather the visible context for evaluation.
TimingExprLet * let
Context visible as sub expressions.
std::vector< uint64_t > results
std::vector< bool > resultAvailable
TimingExprEvalContext(const StaticInstPtr &inst_, ThreadContext *thread_, TimingExprLet *let_)
const StaticInstPtr & inst
Special visible context.
uint64_t eval(TimingExprEvalContext &context)
std::vector< TimingExpr * > defns
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
uint64_t eval(TimingExprEvalContext &context)
virtual uint64_t eval(TimingExprEvalContext &context)=0
static constexpr int ceilLog2(const T &n)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....