sim_object.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2015, 2021 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * Copyright (c) 2010 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/* @file
 * User Console Definitions
 */
 
#ifndef __SIM_OBJECT_HH__
#define __SIM_OBJECT_HH__
 
#include <string>
#include <vector>
 
#include "base/named.hh"
#include "base/stats/group.hh"
#include "params/SimObject.hh"
#include "sim/drain.hh"
#include "sim/eventq.hh"
#include "sim/port.hh"
#include "sim/serialize.hh"
 
namespace gem5
{
 
class EventManager;
class ProbeManager;
class SimObjectResolver;
 
class SimObject : public EventManager, public Serializable, public Drainable,
                  public statistics::Group, public Named
{
  private:
    typedef std::vector<SimObject *> SimObjectList;
 
    static SimObjectList simObjectList;
 
    static SimObjectResolver *_objNameResolver;
 
    ProbeManager *probeManager;
 
  protected:
    const SimObjectParams &_params;
 
  public:
    typedef SimObjectParams Params;
    const Params &params() const { return _params; }
 
    SimObject(const Params &p);
 
    virtual ~SimObject();
 
  public:
    virtual void init();
 
    virtual void loadState(CheckpointIn &cp);
 
    virtual void initState();
 
    virtual void regProbePoints();
 
    virtual void regProbeListeners();
 
    ProbeManager *getProbeManager();
 
    virtual Port &getPort(const std::string &if_name,
                          PortID idx=InvalidPortID);
 
    virtual void startup();
 
    DrainState drain() override { return DrainState::Drained; }
 
    virtual void memWriteback() {};
 
    virtual void memInvalidate() {};
 
    void serialize(CheckpointOut &cp) const override {};
    void unserialize(CheckpointIn &cp) override {};
 
    static void serializeAll(const std::string &cpt_dir);
 
    static SimObject *find(const char *name);
 
    static void setSimObjectResolver(SimObjectResolver *resolver);
 
    static SimObjectResolver *getSimObjectResolver();
};
 
/* Add PARAMS(ClassName) to every descendant of SimObject that needs
 * params.
 *
 * Strictly speaking, we need static_cast here, because the types are
 * related by inheritance, but since the target type may be
 * incomplete, the compiler does not know the relation.
 */
#define PARAMS(type)                                     \
    using Params = type ## Params;                       \
    const Params &                                       \
    params() const                                       \
    {                                                    \
        return reinterpret_cast<const Params&>(_params); \
    }
 
class SimObjectResolver
{
  public:
    virtual ~SimObjectResolver() { }
 
    virtual SimObject *resolveSimObject(const std::string &name) = 0;
};
 
 
void objParamIn(CheckpointIn &cp, const std::string &name, SimObject * &param);
 
void debug_serialize(const std::string &cpt_dir);
 
} // namespace gem5
 
#endif // __SIM_OBJECT_HH__