42 #ifndef __CPU_EXEC_CONTEXT_HH__ 43 #define __CPU_EXEC_CONTEXT_HH__ 45 #include "arch/registers.hh" 47 #include "config/the_isa.hh" 219 virtual PCState
pcState()
const = 0;
238 panic(
"ExecContext::readMem() should be overridden\n");
252 panic(
"ExecContext::initiateMemRead() should be overridden\n");
272 panic(
"ExecContext::amoMem() should be overridden\n");
283 panic(
"ExecContext::initiateMemAMO() should be overridden\n");
342 #endif // __CPU_EXEC_CONTEXT_HH__ #define panic(...)
This implements a cprintf based panic() function.
virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx)=0
Reads a floating point register in its binary format, instead of by value.
virtual void setIntRegOperand(const StaticInst *si, int idx, RegVal val)=0
Sets an integer register to a value.
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register...
virtual RegVal readIntRegOperand(const StaticInst *si, int idx)=0
Reads an integer register.
virtual void setPredicate(bool val)=0
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) ...
virtual bool readMemAccPredicate() const =0
virtual VecElem readVecElemOperand(const StaticInst *si, int idx) const =0
Vector Elem Interfaces.
virtual ConstVecLane32 readVec32BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 32bit operand.
virtual void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)=0
Sets the bits of a floating point register of single width to a binary value.
Vector Register Abstraction This generic class is the model in a particularization of MVC...
virtual VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx)=0
Gets destination vector register operand for modification.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Initiate a timing memory read operation.
virtual PCState pcState() const =0
virtual ConstVecLane8 readVec8BitLaneOperand(const StaticInst *si, int idx) const =0
Vector Register Lane Interfaces.
virtual void demapPage(Addr vaddr, uint64_t asn)=0
Invalidate a page in the DTLB and ITLB.
virtual void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)=0
Sets a vector register to a value.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx)=0
Gets destination predicate register operand for modification.
virtual RegVal readCCRegOperand(const StaticInst *si, int idx)=0
virtual void setStCondFailures(unsigned int sc_failures)=0
Sets the number of consecutive store conditional failures.
virtual bool mwait(PacketPtr pkt)=0
virtual void mwaitAtomic(ThreadContext *tc)=0
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())=0
For atomic-mode contexts, perform an atomic memory write operation.
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
VecPredReg::Container VecPredRegContainer
virtual const VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const =0
Vector Register Interfaces.
virtual void armMonitor(Addr address)=0
virtual ConstVecLane16 readVec16BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 16bit operand.
virtual void setCCRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val)=0
Write a lane of the destination vector operand.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx)=0
virtual unsigned int readStCondFailures() const =0
Returns the number of consecutive store conditional failures.
virtual AddressMonitor * getAddrMonitor()=0
VecReg::Container VecRegContainer
virtual ConstVecLane64 readVec64BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 64bit operand.
virtual void syscall(Fault *fault)=0
Executes a syscall.
Generic predicate register container.
virtual const VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const =0
Predicate registers interface.
Base, ISA-independent static instruction class.
virtual void setMemAccPredicate(bool val)=0
Vector Lane abstraction Another view of a container.
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Perform an atomic memory read operation.
GenericISA::DelaySlotPCState< MachInst > PCState
std::shared_ptr< FaultBase > Fault
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register...
virtual Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) ...
virtual void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val)=0
Sets a destination vector register operand to a value.
virtual void setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val)=0
Sets a destination predicate register operand to a value.
virtual bool readPredicate() const =0