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exec_context.hh
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41 
42 #ifndef __CPU_EXEC_CONTEXT_HH__
43 #define __CPU_EXEC_CONTEXT_HH__
44 
45 #include "arch/registers.hh"
46 #include "base/types.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "cpu/reg_class.hh"
50 #include "cpu/static_inst_fwd.hh"
51 #include "cpu/translation.hh"
52 #include "mem/request.hh"
53 
70 class ExecContext {
71  public:
73 
77 
78  public:
86  virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
87 
89  virtual void setIntRegOperand(const StaticInst *si,
90  int idx, RegVal val) = 0;
91 
102  virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
103 
106  virtual void setFloatRegOperandBits(const StaticInst *si,
107  int idx, RegVal val) = 0;
108 
114  virtual const VecRegContainer&
115  readVecRegOperand(const StaticInst *si, int idx) const = 0;
116 
118  virtual VecRegContainer&
119  getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
120 
122  virtual void
123  setVecRegOperand(const StaticInst *si, int idx,
124  const VecRegContainer& val) = 0;
130  virtual ConstVecLane8
131  readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
132 
134  virtual ConstVecLane16
135  readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
136 
138  virtual ConstVecLane32
139  readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
140 
142  virtual ConstVecLane64
143  readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
144 
147  virtual void setVecLaneOperand(const StaticInst *si, int idx,
148  const LaneData<LaneSize::Byte>& val) = 0;
149  virtual void setVecLaneOperand(const StaticInst *si, int idx,
150  const LaneData<LaneSize::TwoByte>& val) = 0;
151  virtual void setVecLaneOperand(const StaticInst *si, int idx,
152  const LaneData<LaneSize::FourByte>& val) = 0;
153  virtual void setVecLaneOperand(const StaticInst *si, int idx,
160  virtual VecElem readVecElemOperand(const StaticInst *si,
161  int idx) const = 0;
162 
164  virtual void setVecElemOperand(const StaticInst *si, int idx,
165  const VecElem val) = 0;
171  virtual const VecPredRegContainer&
172  readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
173 
175  virtual VecPredRegContainer&
176  getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
177 
179  virtual void
180  setVecPredRegOperand(const StaticInst *si, int idx,
181  const VecPredRegContainer& val) = 0;
188  virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
189  virtual void setCCRegOperand(
190  const StaticInst *si, int idx, RegVal val) = 0;
197  virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
198  virtual void setMiscRegOperand(const StaticInst *si,
199  int idx, RegVal val) = 0;
200 
205  virtual RegVal readMiscReg(int misc_reg) = 0;
206 
211  virtual void setMiscReg(int misc_reg, RegVal val) = 0;
212 
219  virtual PCState pcState() const = 0;
220  virtual void pcState(const PCState &val) = 0;
234  virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
235  Request::Flags flags,
236  const std::vector<bool>& byte_enable = std::vector<bool>())
237  {
238  panic("ExecContext::readMem() should be overridden\n");
239  }
240 
248  virtual Fault initiateMemRead(Addr addr, unsigned int size,
249  Request::Flags flags,
250  const std::vector<bool>& byte_enable = std::vector<bool>())
251  {
252  panic("ExecContext::initiateMemRead() should be overridden\n");
253  }
254 
259  virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
260  Request::Flags flags, uint64_t *res,
261  const std::vector<bool>& byte_enable =
262  std::vector<bool>()) = 0;
263 
268  virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
269  Request::Flags flags,
270  AtomicOpFunctorPtr amo_op)
271  {
272  panic("ExecContext::amoMem() should be overridden\n");
273  }
274 
279  virtual Fault initiateMemAMO(Addr addr, unsigned int size,
280  Request::Flags flags,
281  AtomicOpFunctorPtr amo_op)
282  {
283  panic("ExecContext::initiateMemAMO() should be overridden\n");
284  }
285 
289  virtual void setStCondFailures(unsigned int sc_failures) = 0;
290 
294  virtual unsigned int readStCondFailures() const = 0;
295 
306  virtual void syscall(Fault *fault) = 0;
307 
311  virtual ThreadContext *tcBase() const = 0;
312 
318  virtual bool readPredicate() const = 0;
319  virtual void setPredicate(bool val) = 0;
320  virtual bool readMemAccPredicate() const = 0;
321  virtual void setMemAccPredicate(bool val) = 0;
322 
333  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
334  virtual void armMonitor(Addr address) = 0;
335  virtual bool mwait(PacketPtr pkt) = 0;
336  virtual void mwaitAtomic(ThreadContext *tc) = 0;
337  virtual AddressMonitor *getAddrMonitor() = 0;
338 
340 };
341 
342 #endif // __CPU_EXEC_CONTEXT_HH__
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:163
virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx)=0
Reads a floating point register in its binary format, instead of by value.
virtual void setIntRegOperand(const StaticInst *si, int idx, RegVal val)=0
Sets an integer register to a value.
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register...
virtual RegVal readIntRegOperand(const StaticInst *si, int idx)=0
Reads an integer register.
virtual void setPredicate(bool val)=0
virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) ...
virtual bool readMemAccPredicate() const =0
virtual VecElem readVecElemOperand(const StaticInst *si, int idx) const =0
Vector Elem Interfaces.
virtual ConstVecLane32 readVec32BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 32bit operand.
virtual void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)=0
Sets the bits of a floating point register of single width to a binary value.
Vector Register Abstraction This generic class is the model in a particularization of MVC...
Definition: vec_reg.hh:156
virtual VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx)=0
Gets destination vector register operand for modification.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
ip6_addr_t addr
Definition: inet.hh:330
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:228
virtual Fault initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Initiate a timing memory read operation.
virtual PCState pcState() const =0
TheISA::PCState PCState
Definition: exec_context.hh:72
virtual ConstVecLane8 readVec8BitLaneOperand(const StaticInst *si, int idx) const =0
Vector Register Lane Interfaces.
uint64_t RegVal
Definition: types.hh:166
virtual void demapPage(Addr vaddr, uint64_t asn)=0
Invalidate a page in the DTLB and ITLB.
uint32_t VecElem
Definition: registers.hh:68
virtual void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)=0
Sets a vector register to a value.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx)=0
Gets destination predicate register operand for modification.
virtual RegVal readCCRegOperand(const StaticInst *si, int idx)=0
virtual void setStCondFailures(unsigned int sc_failures)=0
Sets the number of consecutive store conditional failures.
Bitfield< 63 > val
Definition: misc.hh:769
Bitfield< 15, 0 > si
Definition: types.hh:53
virtual bool mwait(PacketPtr pkt)=0
virtual void mwaitAtomic(ThreadContext *tc)=0
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())=0
For atomic-mode contexts, perform an atomic memory write operation.
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
Definition: vec_reg.hh:458
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:70
VecPredReg::Container VecPredRegContainer
Definition: registers.hh:77
virtual const VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const =0
Vector Register Interfaces.
virtual void armMonitor(Addr address)=0
virtual ConstVecLane16 readVec16BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 16bit operand.
virtual void setCCRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val)=0
Write a lane of the destination vector operand.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:249
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx)=0
virtual unsigned int readStCondFailures() const =0
Returns the number of consecutive store conditional failures.
virtual AddressMonitor * getAddrMonitor()=0
VecReg::Container VecRegContainer
Definition: registers.hh:71
virtual ConstVecLane64 readVec64BitLaneOperand(const StaticInst *si, int idx) const =0
Reads source vector 64bit operand.
virtual void syscall(Fault *fault)=0
Executes a syscall.
Generic predicate register container.
Definition: vec_pred_reg.hh:47
virtual const VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const =0
Predicate registers interface.
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
virtual void setMemAccPredicate(bool val)=0
Vector Lane abstraction Another view of a container.
Definition: vec_reg.hh:262
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
Perform an atomic memory read operation.
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
TheISA::VecElem VecElem
Definition: exec_context.hh:75
const char data[]
std::shared_ptr< FaultBase > Fault
Definition: types.hh:238
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register...
virtual Fault initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) ...
virtual void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val)=0
Sets a destination vector register operand to a value.
virtual void setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0
virtual void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val)=0
Sets a destination predicate register operand to a value.
virtual bool readPredicate() const =0

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