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generic_timer.hh
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37 
38 #ifndef __DEV_ARM_GENERIC_TIMER_HH__
39 #define __DEV_ARM_GENERIC_TIMER_HH__
40 
41 #include "arch/arm/isa_device.hh"
42 #include "arch/arm/system.hh"
43 #include "dev/arm/base_gic.hh"
45 #include "sim/core.hh"
46 #include "sim/sim_object.hh"
47 
56 
57 class Checkpoint;
58 class SystemCounterParams;
59 class GenericTimerParams;
60 class GenericTimerFrameParams;
61 class GenericTimerMemParams;
62 
66 {
67  public:
70  virtual void notify(void) = 0;
71 };
72 
75 class SystemCounter : public SimObject
76 {
77  protected:
79  bool _enabled;
81  uint32_t _freq;
83  uint64_t _value;
85  uint64_t _increment;
95 
98 
100  static constexpr size_t MAX_FREQ_ENTRIES = 1004;
101 
102  public:
103  SystemCounter(SystemCounterParams *const p);
104 
107  static void validateCounterRef(SystemCounter *sys_cnt);
108 
110  bool enabled() const { return _enabled; }
112  uint32_t freq() const { return _freq; }
114  uint64_t value();
116  uint64_t increment() const { return _increment; }
118  std::vector<uint32_t>& freqTable() { return _freqTable; }
120  size_t activeFreqEntry() const { return _activeFreqEntry; }
122  Tick period() const { return _period; }
123 
125  void enable();
127  void disable();
128 
132  void freqUpdateSchedule(size_t new_freq_entry);
133 
135  void setValue(uint64_t new_value);
136 
138  void registerListener(SystemCounterListener *listener);
139 
141  Tick whenValue(uint64_t target_val);
142  Tick whenValue(uint64_t cur_val, uint64_t target_val) const;
143 
144  void serialize(CheckpointOut &cp) const override;
145  void unserialize(CheckpointIn &cp) override;
146 
147  private:
148  // Disable copying
149  SystemCounter(const SystemCounter &c);
150 
155  void freqUpdateCallback();
156 
158  void updateValue(void);
159 
161  void updateTick(void);
162 
164  void notifyListeners(void) const;
165 };
166 
169 {
170  protected:
172  BitUnion32(ArchTimerCtrl)
173  Bitfield<0> enable;
174  Bitfield<1> imask;
175  Bitfield<2> istatus;
176  EndBitUnion(ArchTimerCtrl)
177 
178 
179  const std::string _name;
180 
183 
185 
187 
189  ArchTimerCtrl _control;
191  uint64_t _counterLimit;
193  uint64_t _offset;
194 
199  void updateCounter();
200 
202  void counterLimitReached();
204 
205  virtual bool scheduleEvents() { return true; }
206 
207  public:
208  ArchTimer(const std::string &name,
209  SimObject &parent,
210  SystemCounter &sysctr,
211  ArmInterruptPin *interrupt);
212 
214  std::string name() const { return _name; }
215 
217  uint64_t compareValue() const { return _counterLimit; }
219  void setCompareValue(uint64_t val);
220 
222  uint32_t timerValue() const { return _counterLimit - value(); }
224  void setTimerValue(uint32_t val);
225 
227  uint32_t control() const { return _control; }
228  void setControl(uint32_t val);
229 
230  uint64_t offset() const { return _offset; }
231  void setOffset(uint64_t val);
232 
234  uint64_t value() const;
235  Tick whenValue(uint64_t target_val) {
236  return _systemCounter.whenValue(value(), target_val);
237  }
238 
239  void notify(void) override;
240 
241  // Serializable
242  void serialize(CheckpointOut &cp) const override;
243  void unserialize(CheckpointIn &cp) override;
244 
245  // Drainable
246  DrainState drain() override;
247  void drainResume() override;
248 
249  private:
250  // Disable copying
251  ArchTimer(const ArchTimer &t);
252 };
253 
254 class ArchTimerKvm : public ArchTimer
255 {
256  private:
258 
259  public:
260  ArchTimerKvm(const std::string &name,
261  ArmSystem &system,
262  SimObject &parent,
263  SystemCounter &sysctr,
264  ArmInterruptPin *interrupt)
265  : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
266 
267  protected:
268  // For ArchTimer's in a GenericTimerISA with Kvm execution about
269  // to begin, skip rescheduling the event.
270  // Otherwise, we should reschedule the event (if necessary).
271  bool scheduleEvents() override {
272  return !system.validKvmEnvironment();
273  }
274 };
275 
276 class GenericTimer : public SimObject
277 {
278  public:
279  const GenericTimerParams * params() const;
280 
281  GenericTimer(GenericTimerParams *const p);
282 
283  void serialize(CheckpointOut &cp) const override;
284  void unserialize(CheckpointIn &cp) override;
285 
286  public:
287  void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
288  RegVal readMiscReg(int misc_reg, unsigned cpu);
289 
290  protected:
292  {
293  public:
294  CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu,
295  ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
296  ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp);
297 
300 
302  uint32_t cntfrq;
303 
305  CNTKCTL cntkctl;
306 
308  CNTHCTL cnthctl;
309 
312 
317 
322 
323  // Event Stream. Events are generated based on a configurable
324  // transitionBit over the counter value. transitionTo indicates
325  // the transition direction (0->1 or 1->0)
326  struct EventStream
327  {
329  uint8_t transitionTo;
330  uint8_t transitionBit;
331 
332  uint64_t
333  eventTargetValue(uint64_t val) const
334  {
335  uint64_t bit_val = bits(val, transitionBit);
336  uint64_t ret_val = mbits(val, 63, transitionBit);
337  uint64_t incr_val = 1 << transitionBit;
338  if (bit_val == transitionTo)
339  incr_val *= 2;
340  return ret_val + incr_val;
341  }
342  };
343 
346  void physEventStreamCallback();
347  void virtEventStreamCallback();
348  void eventStreamCallback() const;
349  void schedNextEvent(EventStream &ev_stream, ArchTimer &timer);
350 
351  void notify(void) override;
352 
353  void serialize(CheckpointOut &cp) const override;
354  void unserialize(CheckpointIn &cp) override;
355 
356  private:
357  // Disable copying
358  CoreTimers(const CoreTimers &c);
359  };
360 
361  CoreTimers &getTimers(int cpu_id);
362  void createTimers(unsigned cpus);
363 
366 
369 
370  protected: // Configuration
373 
374  void handleStream(CoreTimers::EventStream *ev_stream,
375  ArchTimer *timer, RegVal old_cnt_ctl, RegVal cnt_ctl);
376 };
377 
379 {
380  public:
381  GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
382  : parent(_parent), cpu(_cpu) {}
383 
384  void setMiscReg(int misc_reg, RegVal val) override;
385  RegVal readMiscReg(int misc_reg) override;
386 
387  protected:
389  unsigned cpu;
390 };
391 
393 {
394  public:
395  GenericTimerFrame(GenericTimerFrameParams *const p);
396 
397  void serialize(CheckpointOut &cp) const override;
398  void unserialize(CheckpointIn &cp) override;
399 
401  bool hasVirtualTimer() const;
402 
405  uint64_t getVirtOffset() const;
406 
409  void setVirtOffset(uint64_t new_offset);
410 
412  bool hasEl0View() const;
413 
415  uint8_t getAccessBits() const;
416 
418  void setAccessBits(uint8_t data);
419 
421  bool hasNonSecureAccess() const;
422 
425  void setNonSecureAccess();
426 
428  bool hasReadableVoff() const;
429 
430  protected:
431  AddrRangeList getAddrRanges() const override;
432  Tick read(PacketPtr pkt) override;
433  Tick write(PacketPtr pkt) override;
434 
435  private:
437  uint64_t timerRead(Addr addr, size_t size, bool is_sec, bool to_el0) const;
438  void timerWrite(Addr addr, size_t size, uint64_t data, bool is_sec,
439  bool to_el0);
442 
443  static const Addr TIMER_CNTPCT_LO = 0x00;
444  static const Addr TIMER_CNTPCT_HI = 0x04;
445  static const Addr TIMER_CNTVCT_LO = 0x08;
446  static const Addr TIMER_CNTVCT_HI = 0x0c;
447  static const Addr TIMER_CNTFRQ = 0x10;
448  static const Addr TIMER_CNTEL0ACR = 0x14;
449  static const Addr TIMER_CNTVOFF_LO = 0x18;
450  static const Addr TIMER_CNTVOFF_HI = 0x1c;
451  static const Addr TIMER_CNTP_CVAL_LO = 0x20;
452  static const Addr TIMER_CNTP_CVAL_HI = 0x24;
453  static const Addr TIMER_CNTP_TVAL = 0x28;
454  static const Addr TIMER_CNTP_CTL = 0x2c;
455  static const Addr TIMER_CNTV_CVAL_LO = 0x30;
456  static const Addr TIMER_CNTV_CVAL_HI = 0x34;
457  static const Addr TIMER_CNTV_TVAL = 0x38;
458  static const Addr TIMER_CNTV_CTL = 0x3c;
459 
462 
465 
469 
471  BitUnion8(AccessBits)
472  Bitfield<5> rwpt;
473  Bitfield<4> rwvt;
474  Bitfield<3> rvoff;
475  Bitfield<2> rfrq;
476  Bitfield<1> rvct;
477  Bitfield<0> rpct;
478  EndBitUnion(AccessBits)
479  AccessBits accessBits;
480 
481  // Reports access properties of the CNTEL0Base register frame elements
482  BitUnion16(AccessBitsEl0)
483  Bitfield<9> pten;
484  Bitfield<8> vten;
485  Bitfield<1> vcten;
486  Bitfield<0> pcten;
487  EndBitUnion(AccessBitsEl0)
488  AccessBitsEl0 accessBitsEl0;
489 
492 
494 };
495 
497 {
498  public:
499  GenericTimerMem(GenericTimerMemParams *const p);
500 
503  static void validateFrameRange(const AddrRange &range);
504 
508  static bool validateAccessPerm(ArmSystem &sys, bool is_sec);
509 
510  protected:
511  AddrRangeList getAddrRanges() const override;
512  Tick read(PacketPtr pkt) override;
513  Tick write(PacketPtr pkt) override;
514 
515  private:
517  uint64_t counterCtrlRead(Addr addr, size_t size, bool is_sec) const;
518  void counterCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
520 
521  BitUnion32(CNTCR)
522  Bitfield<17,8> fcreq;
523  Bitfield<2> scen;
524  Bitfield<1> hdbg;
525  Bitfield<0> en;
526  EndBitUnion(CNTCR)
527 
528  BitUnion32(CNTSR)
529  Bitfield<31,8> fcack;
530  EndBitUnion(CNTSR)
531 
532  static const Addr COUNTER_CTRL_CNTCR = 0x00;
533  static const Addr COUNTER_CTRL_CNTSR = 0x04;
534  static const Addr COUNTER_CTRL_CNTCV_LO = 0x08;
535  static const Addr COUNTER_CTRL_CNTCV_HI = 0x0c;
536  static const Addr COUNTER_CTRL_CNTSCR = 0x10;
537  static const Addr COUNTER_CTRL_CNTID = 0x1c;
538  static const Addr COUNTER_CTRL_CNTFID = 0x20;
539 
541  uint64_t counterStatusRead(Addr addr, size_t size) const;
542  void counterStatusWrite(Addr addr, size_t size, uint64_t data);
543  const AddrRange counterStatusRange;
544 
545  static const Addr COUNTER_STATUS_CNTCV_LO = 0x00;
546  static const Addr COUNTER_STATUS_CNTCV_HI = 0x04;
547 
549  uint64_t timerCtrlRead(Addr addr, size_t size, bool is_sec) const;
550  void timerCtrlWrite(Addr addr, size_t size, uint64_t data, bool is_sec);
551  const AddrRange timerCtrlRange;
552 
554  uint32_t cnttidr;
555 
556  static const Addr TIMER_CTRL_CNTFRQ = 0x00;
557  static const Addr TIMER_CTRL_CNTNSAR = 0x04;
558  static const Addr TIMER_CTRL_CNTTIDR = 0x08;
559  static const Addr TIMER_CTRL_CNTACR = 0x40;
560  static const Addr TIMER_CTRL_CNTVOFF_LO = 0x80;
561  static const Addr TIMER_CTRL_CNTVOFF_HI = 0x84;
562 
564  const AddrRangeList addrRanges;
565 
567  SystemCounter &systemCounter;
568 
570  static constexpr size_t MAX_TIMER_FRAMES = 8;
571 
574 
576 };
577 
578 #endif // __DEV_ARM_GENERIC_TIMER_HH__
const AddrRange counterCtrlRange
EventFunctionWrapper _counterLimitReachedEvent
uint64_t offset() const
Bitfield< 0 > rpct
uint64_t _counterLimit
Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
std::vector< uint32_t > _freqTable
Frequency modes table with all possible frequencies for the counter.
std::vector< SystemCounterListener * > _listeners
Listeners to changes in counting speed.
ArmInterruptPin const * irqPhysNS
ArmInterruptPin const * irqVirt
Tick _updateTick
Counter cycle start Tick when the counter status affecting its value has been updated.
const std::string & name()
Definition: trace.cc:50
EndBitUnion(UserDescFlags) struct UserDesc32
Definition: process.cc:152
ArmInterruptPin const * irqPhysS
SystemCounter & systemCounter
System counter reference.
CNTKCTL cntkctl
Kernel control register.
Per-CPU architected timer.
ThreadContext * threadContext
Thread (HW) context associated to this PE implementation.
ip6_addr_t addr
Definition: inet.hh:330
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:58
uint64_t RegVal
Definition: types.hh:166
size_t _nextFreqEntry
uint32_t cntfrq
System counter frequency as visible from this core.
const AddrRange timerRange
uint32_t freq() const
Returns the counter frequency.
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
SystemCounter & systemCounter
System counter reference.
bool _enabled
Definition: statistics.cc:542
Definition: cprintf.cc:40
Bitfield< 30 > en
ArmSystem & system
Bitfield< 1 > imask
ThreadContext is the external interface to all thread state for anything outside of the CPU...
ArmSystem & system
ARM system containing this timer.
Bitfield< 8 > vten
DrainState
Object drain/handover states.
Definition: drain.hh:71
Bitfield< 63 > val
Definition: misc.hh:769
ArchTimerCtrl _control
Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
bool enabled() const
Indicates if the counter is enabled.
Tick _period
Cached copy of the counter period (inverse of the frequency).
Interface for objects that might require draining before checkpointing.
Definition: drain.hh:239
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:68
virtual void serialize(CheckpointOut &cp) const =0
Serialize an object.
Bitfield< 11 > enable
Definition: misc.hh:1051
bool scheduleEvents() override
EventFunctionWrapper _freqUpdateEvent
Frequency update event handling.
uint64_t eventTargetValue(uint64_t val) const
uint64_t Tick
Tick count type.
Definition: types.hh:61
ArmSystem & system
AddrRangeList addrRanges
All MMIO ranges GenericTimerFrame responds to.
size_t activeFreqEntry() const
Returns the currently active frequency table entry.
uint32_t timerValue() const
Returns the TimerValue view of the timer.
This device is the base class which all devices senstive to an address range inherit from...
Definition: io_device.hh:99
AddrRange timerEl0Range
#define BitUnion16(name)
Definition: bitunion.hh:376
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
bool nonSecureAccess
Reports whether non-secure accesses are allowed to this frame.
virtual bool scheduleEvents()
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:249
Bitfield< 15, 8 > vector
Definition: intmessage.hh:44
Basic support for object serialization.
Definition: serialize.hh:166
Tick whenValue(uint64_t target_val)
Bitfield< 3 > rvoff
Bitfield< 15 > system
Definition: misc.hh:997
#define BitUnion8(name)
Definition: bitunion.hh:377
Abstract class for elements whose events depend on the counting speed of the System Counter...
virtual void unserialize(CheckpointIn &cp)=0
Unserialize an object.
bool validKvmEnvironment() const
Verify gem5 configuration will support KVM emulation.
Definition: system.cc:305
std::string name() const
Returns the timer name.
Bitfield< 4 > rwvt
Bitfield< 29 > c
Base class for ARM GIC implementations.
std::ostream CheckpointOut
Definition: serialize.hh:63
Tick whenValue(uint64_t target_val)
Returns the tick at which a certain counter value is reached.
GenericTimer & parent
Bitfield< 2 > istatus
uint64_t compareValue() const
Returns the CompareValue view of the timer.
ArmInterruptPin *const _interrupt
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
Bitfield< 0 > pcten
uint64_t _value
Counter value (as specified in CNTCV).
std::vector< std::unique_ptr< CoreTimers > > timers
Per-CPU physical architected timers.
ArmInterruptPin const * irqHyp
uint64_t increment() const
Returns the value increment.
bool _enabled
Indicates if the counter is enabled.
BitUnion32(UserDescFlags) Bitfield< 0 > seg_32bit
Bitfield< 5 > t
SystemCounter & _systemCounter
ArchTimerKvm(const std::string &name, ArmSystem &system, SimObject &parent, SystemCounter &sysctr, ArmInterruptPin *interrupt)
T mbits(T val, int first, int last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:95
T bits(T val, int first, int last)
Extract the bitfield from position &#39;first&#39; to &#39;last&#39; (inclusive) from &#39;val&#39; and right justify it...
Definition: bitfield.hh:71
uint32_t control() const
Sets the control register.
size_t _activeFreqEntry
Currently selected entry in the table, its contents should match _freq.
Bitfield< 2 > rfrq
Global system counter.
Bitfield< 0 > p
virtual void notify(void)=0
Called from the SystemCounter when a change in counting speed occurred Events should be rescheduled p...
std::vector< uint32_t > & freqTable()
Returns a reference to the frequency modes table.
const char data[]
CNTHCTL cnthctl
Hypervisor control register.
Bitfield< 1 > rvct
GenericTimer & parent
Generic Timer parent reference.
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:176
Tick period() const
Returns the counter period.
Abstract superclass for simulation objects.
Definition: sim_object.hh:92
uint32_t _freq
Counter frequency (as specified by CNTFRQ).
ArchTimer physTimer
Physical and virtual timers.
uint64_t _increment
Value increment in each counter cycle.
uint64_t _offset
Offset relative to the physical timer (CNTVOFF)
Bitfield< 1 > vcten
EndBitUnion(ArchTimerCtrl) const std SimObject & _parent
Name of this timer.
void disable()
Definition: trace.cc:98

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