42 #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 43 #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 46 #include "arch/kernel_stats.hh" 47 #include "arch/registers.hh" 48 #include "config/the_isa.hh" 51 #include "debug/O3CPU.hh" 57 return thread->getVirtProxy();
64 thread->dumpFuncProfile();
73 this->getIsaPtr()->takeOverFrom(
this, old_context);
75 TheISA::Decoder *newDecoder = getDecoderPtr();
77 newDecoder->takeOverFrom(oldDecoder);
82 thread->noSquashFromTC =
false;
83 thread->trapPending =
false;
90 DPRINTF(
O3CPU,
"Calling activate on Thread Context %d\n",
96 thread->lastActivate =
curTick();
100 cpu->activateContext(thread->threadId());
103 template <
class Impl>
107 DPRINTF(
O3CPU,
"Calling suspend on Thread Context %d\n",
113 if (cpu->isDraining()) {
114 DPRINTF(
O3CPU,
"Ignoring suspend on TC due to pending drain\n");
118 thread->lastActivate =
curTick();
119 thread->lastSuspend =
curTick();
122 cpu->suspendContext(thread->threadId());
125 template <
class Impl>
129 DPRINTF(
O3CPU,
"Calling halt on Thread Context %d\n", threadId());
142 cpu->addThreadToExitingList(thread->threadId());
145 template <
class Impl>
150 thread->kernelStats =
new TheISA::Kernel::Statistics();
151 thread->kernelStats->regStats(name +
".kern");
155 template <
class Impl>
159 return thread->lastActivate;
162 template <
class Impl>
166 return thread->lastSuspend;
169 template <
class Impl>
173 thread->profileClear();
176 template <
class Impl>
180 thread->profileSample();
183 template <
class Impl>
191 thread->noSquashFromTC =
true;
193 thread->noSquashFromTC =
false;
199 template <
class Impl>
203 cpu->isa[thread->threadId()]->clear(
this);
206 template <
class Impl>
210 return cpu->readArchIntReg(reg_idx, thread->threadId());
213 template <
class Impl>
217 return cpu->readArchFloatReg(reg_idx, thread->threadId());
220 template <
class Impl>
224 return cpu->readArchVecReg(reg_id, thread->threadId());
227 template <
class Impl>
231 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
234 template <
class Impl>
239 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
242 template <
class Impl>
246 return cpu->readArchVecPredReg(reg_id, thread->threadId());
249 template <
class Impl>
253 return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
256 template <
class Impl>
260 return cpu->readArchCCReg(reg_idx, thread->threadId());
263 template <
class Impl>
267 cpu->setArchIntReg(reg_idx, val, thread->threadId());
272 template <
class Impl>
276 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
281 template <
class Impl>
286 cpu->setArchVecReg(reg_idx, val, thread->threadId());
291 template <
class Impl>
296 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
300 template <
class Impl>
305 cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
310 template <
class Impl>
314 cpu->setArchCCReg(reg_idx, val, thread->threadId());
319 template <
class Impl>
323 cpu->pcState(val, thread->threadId());
328 template <
class Impl>
332 cpu->pcState(val, thread->threadId());
337 template <
class Impl>
341 return cpu->isa[thread->threadId()]->flattenRegId(regId);
344 template <
class Impl>
348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
353 template <
class Impl>
357 cpu->setMiscReg(misc_reg, val, thread->threadId());
362 #endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__ Tick readLastActivate() override
Reads the last tick that this thread was activated on.
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const VecElem &val) override
virtual TheISA::Decoder * getDecoderPtr()=0
const std::string & name()
PortProxy & getVirtProxy() override
Trying to exit and waiting for an event to completely exit.
Vector Register Abstraction This generic class is the model in a particularization of MVC...
virtual TheISA::PCState pcState() const =0
void setFloatRegFlat(RegIndex idx, RegVal val) override
virtual ::Kernel::Statistics * getKernelStats()=0
void dumpFuncProfile() override
Dumps the function profiling information.
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void pcStateNoRecord(const TheISA::PCState &val) override
void halt() override
Set the status to Halted.
void takeOverFrom(ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
void clearArchRegs() override
Resets all architectural registers to 0.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
void profileClear() override
Clears the function profiling information.
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Tick curTick()
The current simulated tick.
RegVal readCCRegFlat(RegIndex idx) const override
uint64_t Tick
Tick count type.
VecPredReg::Container VecPredRegContainer
void setIntRegFlat(RegIndex idx, RegVal val) override
virtual Counter readFuncExeInst() const =0
TheISA::PCState pcState() const override
Reads this thread's PC state.
VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register operand for modification, flat indexing.
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
void suspend() override
Set the status to Suspended.
const VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
This object is a proxy for a port or other object which implements the functional response protocol...
VecReg::Container VecRegContainer
uint16_t ElemIndex
Logical vector register elem index type.
void regStats(const std::string &name) override
Registers statistics associated with this TC.
const VecRegContainer & readVecRegFlat(RegIndex idx) const override
Generic predicate register container.
void copyArchRegs(ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
void setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
Helper structure to get the vector register mode for a given ISA.
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Register ID: describe an architectural register with its class and index.
RegVal readFloatRegFlat(RegIndex idx) const override
RegId flattenRegId(const RegId ®Id) const override
void activate() override
Set the status to Active.
void copyRegs(ThreadContext *src, ThreadContext *dest)
GenericISA::DelaySlotPCState< MachInst > PCState
const VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIndex) const override
void setCCRegFlat(RegIndex idx, RegVal val) override
void profileSample() override
Samples the function profiling information.