gem5  v20.0.0.2
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
thread_context_impl.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
43 #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
44 
45 #include "arch/generic/traits.hh"
46 #include "arch/kernel_stats.hh"
47 #include "arch/registers.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/o3/thread_context.hh"
50 #include "cpu/quiesce_event.hh"
51 #include "debug/O3CPU.hh"
52 
53 template <class Impl>
54 PortProxy&
56 {
57  return thread->getVirtProxy();
58 }
59 
60 template <class Impl>
61 void
63 {
64  thread->dumpFuncProfile();
65 }
66 
67 template <class Impl>
68 void
70 {
71  ::takeOverFrom(*this, *old_context);
72 
73  this->getIsaPtr()->takeOverFrom(this, old_context);
74 
75  TheISA::Decoder *newDecoder = getDecoderPtr();
76  TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
77  newDecoder->takeOverFrom(oldDecoder);
78 
79  thread->kernelStats = old_context->getKernelStats();
80  thread->funcExeInst = old_context->readFuncExeInst();
81 
82  thread->noSquashFromTC = false;
83  thread->trapPending = false;
84 }
85 
86 template <class Impl>
87 void
89 {
90  DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
91  threadId());
92 
93  if (thread->status() == ThreadContext::Active)
94  return;
95 
96  thread->lastActivate = curTick();
97  thread->setStatus(ThreadContext::Active);
98 
99  // status() == Suspended
100  cpu->activateContext(thread->threadId());
101 }
102 
103 template <class Impl>
104 void
106 {
107  DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
108  threadId());
109 
110  if (thread->status() == ThreadContext::Suspended)
111  return;
112 
113  if (cpu->isDraining()) {
114  DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
115  return;
116  }
117 
118  thread->lastActivate = curTick();
119  thread->lastSuspend = curTick();
120 
121  thread->setStatus(ThreadContext::Suspended);
122  cpu->suspendContext(thread->threadId());
123 }
124 
125 template <class Impl>
126 void
128 {
129  DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
130 
131  if (thread->status() == ThreadContext::Halting ||
132  thread->status() == ThreadContext::Halted)
133  return;
134 
135  // the thread is not going to halt/terminate immediately in this cycle.
136  // The thread will be removed after an exit trap is processed
137  // (e.g., after trapLatency cycles). Until then, the thread's status
138  // will be Halting.
139  thread->setStatus(ThreadContext::Halting);
140 
141  // add this thread to the exiting list to mark that it is trying to exit.
142  cpu->addThreadToExitingList(thread->threadId());
143 }
144 
145 template <class Impl>
146 void
148 {
149  if (FullSystem) {
150  thread->kernelStats = new TheISA::Kernel::Statistics();
151  thread->kernelStats->regStats(name + ".kern");
152  }
153 }
154 
155 template <class Impl>
156 Tick
158 {
159  return thread->lastActivate;
160 }
161 
162 template <class Impl>
163 Tick
165 {
166  return thread->lastSuspend;
167 }
168 
169 template <class Impl>
170 void
172 {
173  thread->profileClear();
174 }
175 
176 template <class Impl>
177 void
179 {
180  thread->profileSample();
181 }
182 
183 template <class Impl>
184 void
186 {
187  // Set vector renaming mode before copying registers
188  cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
189 
190  // Prevent squashing
191  thread->noSquashFromTC = true;
192  TheISA::copyRegs(tc, this);
193  thread->noSquashFromTC = false;
194 
195  if (!FullSystem)
196  this->thread->funcExeInst = tc->readFuncExeInst();
197 }
198 
199 template <class Impl>
200 void
202 {
203  cpu->isa[thread->threadId()]->clear(this);
204 }
205 
206 template <class Impl>
207 RegVal
209 {
210  return cpu->readArchIntReg(reg_idx, thread->threadId());
211 }
212 
213 template <class Impl>
214 RegVal
216 {
217  return cpu->readArchFloatReg(reg_idx, thread->threadId());
218 }
219 
220 template <class Impl>
223 {
224  return cpu->readArchVecReg(reg_id, thread->threadId());
225 }
226 
227 template <class Impl>
230 {
231  return cpu->getWritableArchVecReg(reg_id, thread->threadId());
232 }
233 
234 template <class Impl>
235 const TheISA::VecElem&
237  const ElemIndex& elemIndex) const
238 {
239  return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
240 }
241 
242 template <class Impl>
245 {
246  return cpu->readArchVecPredReg(reg_id, thread->threadId());
247 }
248 
249 template <class Impl>
252 {
253  return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
254 }
255 
256 template <class Impl>
257 RegVal
259 {
260  return cpu->readArchCCReg(reg_idx, thread->threadId());
261 }
262 
263 template <class Impl>
264 void
266 {
267  cpu->setArchIntReg(reg_idx, val, thread->threadId());
268 
269  conditionalSquash();
270 }
271 
272 template <class Impl>
273 void
275 {
276  cpu->setArchFloatReg(reg_idx, val, thread->threadId());
277 
278  conditionalSquash();
279 }
280 
281 template <class Impl>
282 void
284  RegIndex reg_idx, const VecRegContainer& val)
285 {
286  cpu->setArchVecReg(reg_idx, val, thread->threadId());
287 
288  conditionalSquash();
289 }
290 
291 template <class Impl>
292 void
294  const ElemIndex& elemIndex, const VecElem& val)
295 {
296  cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
297  conditionalSquash();
298 }
299 
300 template <class Impl>
301 void
303  const VecPredRegContainer& val)
304 {
305  cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
306 
307  conditionalSquash();
308 }
309 
310 template <class Impl>
311 void
313 {
314  cpu->setArchCCReg(reg_idx, val, thread->threadId());
315 
316  conditionalSquash();
317 }
318 
319 template <class Impl>
320 void
322 {
323  cpu->pcState(val, thread->threadId());
324 
325  conditionalSquash();
326 }
327 
328 template <class Impl>
329 void
331 {
332  cpu->pcState(val, thread->threadId());
333 
334  conditionalSquash();
335 }
336 
337 template <class Impl>
338 RegId
340 {
341  return cpu->isa[thread->threadId()]->flattenRegId(regId);
342 }
343 
344 template <class Impl>
345 void
347 {
348  cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
349 
350  conditionalSquash();
351 }
352 
353 template <class Impl>
354 void
356 {
357  cpu->setMiscReg(misc_reg, val, thread->threadId());
358 
359  conditionalSquash();
360 }
361 
362 #endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
#define DPRINTF(x,...)
Definition: trace.hh:222
TheISA::VecElem VecElem
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const VecElem &val) override
virtual TheISA::Decoder * getDecoderPtr()=0
const std::string & name()
Definition: trace.cc:50
PortProxy & getVirtProxy() override
Trying to exit and waiting for an event to completely exit.
Vector Register Abstraction This generic class is the model in a particularization of MVC...
Definition: vec_reg.hh:156
virtual TheISA::PCState pcState() const =0
void setFloatRegFlat(RegIndex idx, RegVal val) override
virtual ::Kernel::Statistics * getKernelStats()=0
void dumpFuncProfile() override
Dumps the function profiling information.
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void pcStateNoRecord(const TheISA::PCState &val) override
void halt() override
Set the status to Halted.
void takeOverFrom(ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
uint64_t RegVal
Definition: types.hh:166
void clearArchRegs() override
Resets all architectural registers to 0.
uint32_t VecElem
Definition: registers.hh:68
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
void profileClear() override
Clears the function profiling information.
Bitfield< 63 > val
Definition: misc.hh:769
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Tick curTick()
The current simulated tick.
Definition: core.hh:44
uint16_t RegIndex
Definition: types.hh:40
RegVal readCCRegFlat(RegIndex idx) const override
uint64_t Tick
Tick count type.
Definition: types.hh:61
VecPredReg::Container VecPredRegContainer
Definition: registers.hh:77
void setIntRegFlat(RegIndex idx, RegVal val) override
virtual Counter readFuncExeInst() const =0
TheISA::PCState pcState() const override
Reads this thread&#39;s PC state.
VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Read vector register operand for modification, flat indexing.
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
void suspend() override
Set the status to Suspended.
const VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
This object is a proxy for a port or other object which implements the functional response protocol...
Definition: port_proxy.hh:80
VecReg::Container VecRegContainer
Definition: registers.hh:71
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:43
Permanently shut down.
void regStats(const std::string &name) override
Registers statistics associated with this TC.
const VecRegContainer & readVecRegFlat(RegIndex idx) const override
Generic predicate register container.
Definition: vec_pred_reg.hh:47
Impl::O3CPU O3CPU
void copyArchRegs(ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
void setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
Helper structure to get the vector register mode for a given ISA.
Definition: traits.hh:53
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
Temporarily inactive.
RegVal readFloatRegFlat(RegIndex idx) const override
RegId flattenRegId(const RegId &regId) const override
void activate() override
Set the status to Active.
void copyRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.cc:136
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
const VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIndex) const override
void setCCRegFlat(RegIndex idx, RegVal val) override
void profileSample() override
Samples the function profiling information.

Generated on Mon Jun 8 2020 15:45:09 for gem5 by doxygen 1.8.13