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pagetable_walker.hh
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37 
38 #ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
39 #define __ARCH_X86_PAGE_TABLE_WALKER_HH__
40 
41 #include <vector>
42 
43 #include "arch/x86/pagetable.hh"
44 #include "arch/x86/tlb.hh"
45 #include "base/types.hh"
46 #include "mem/packet.hh"
47 #include "params/X86PagetableWalker.hh"
48 #include "sim/clocked_object.hh"
49 #include "sim/faults.hh"
50 #include "sim/system.hh"
51 
52 class ThreadContext;
53 
54 namespace X86ISA
55 {
56  class Walker : public ClockedObject
57  {
58  protected:
59  // Port for accessing memory
60  class WalkerPort : public MasterPort
61  {
62  public:
63  WalkerPort(const std::string &_name, Walker * _walker) :
64  MasterPort(_name, _walker), walker(_walker)
65  {}
66 
67  protected:
69 
70  bool recvTimingResp(PacketPtr pkt);
71  void recvReqRetry();
72  };
73 
74  friend class WalkerPort;
76 
77  // State to track each walk of the page table
79  {
80  friend class Walker;
81  private:
82  enum State {
85  // Long mode
86  LongPML4, LongPDP, LongPD, LongPTE,
87  // PAE legacy mode
88  PAEPDP, PAEPD, PAEPTE,
89  // Non PAE legacy mode with and without PSE
90  PSEPD, PD, PTE
91  };
92 
93  protected:
99  int dataSize;
100  bool enableNX;
101  unsigned inflight;
109  bool timing;
110  bool retrying;
111  bool started;
112  bool squashed;
113  public:
114  WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
115  const RequestPtr &_req, bool _isFunctional = false) :
116  walker(_walker), req(_req), state(Ready),
117  nextState(Ready), inflight(0),
118  translation(_translation),
119  functional(_isFunctional), timing(false),
120  retrying(false), started(false), squashed(false)
121  {
122  }
123  void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
124  bool _isTiming = false);
125  Fault startWalk();
126  Fault startFunctional(Addr &addr, unsigned &logBytes);
127  bool recvPacket(PacketPtr pkt);
128  unsigned numInflight() const;
129  bool isRetrying();
130  bool wasStarted();
131  bool isTiming();
132  void retry();
133  void squash();
134  std::string name() const {return walker->name();}
135 
136  private:
137  void setupWalk(Addr vaddr);
138  Fault stepWalk(PacketPtr &write);
139  void sendPackets();
140  void endWalk();
141  Fault pageFault(bool present);
142  };
143 
144  friend class WalkerState;
145  // State for timing and atomic accesses (need multiple per walker in
146  // the case of multiple outstanding requests in timing mode)
148  // State for functional accesses (only need one of these per walker)
150 
152  {
155  senderWalk(_senderWalk) {}
156  };
157 
158  public:
159  // Kick off the state machine.
160  Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
161  const RequestPtr &req, BaseTLB::Mode mode);
163  unsigned &logBytes, BaseTLB::Mode mode);
164  Port &getPort(const std::string &if_name,
165  PortID idx=InvalidPortID) override;
166 
167  protected:
168  // The TLB we're supposed to load.
169  TLB * tlb;
172 
173  // The number of outstanding walks that can be squashed per cycle.
174  unsigned numSquashable;
175 
176  // Wrapper for checking for squashes before starting a translation.
177  void startWalkWrapper();
178 
183 
184  // Functions for dealing with packets.
185  bool recvTimingResp(PacketPtr pkt);
186  void recvReqRetry();
187  bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
188 
189  public:
190 
191  void setTLB(TLB * _tlb)
192  {
193  tlb = _tlb;
194  }
195 
196  typedef X86PagetableWalkerParams Params;
197 
198  const Params *
199  params() const
200  {
201  return static_cast<const Params *>(_params);
202  }
203 
204  Walker(const Params *params) :
205  ClockedObject(params), port(name() + ".port", this),
206  funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
207  masterId(sys->getMasterId(this)),
208  numSquashable(params->num_squash_per_cycle),
209  startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
210  {
211  }
212  };
213 }
214 #endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:71
Ports are used to interface objects to each other.
Definition: port.hh:56
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
const PortID InvalidPortID
Definition: types.hh:236
X86PagetableWalkerParams Params
Walker(const Params *params)
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: sim_object.cc:91
std::shared_ptr< Request > RequestPtr
Definition: request.hh:81
WalkerState(Walker *_walker, BaseTLB::Translation *_translation, const RequestPtr &_req, bool _isFunctional=false)
Fault start(ThreadContext *_tc, BaseTLB::Translation *translation, const RequestPtr &req, BaseTLB::Mode mode)
WalkerSenderState(WalkerState *_senderWalk)
WalkerPort(const std::string &_name, Walker *_walker)
Bitfield< 7 > present
Definition: misc.hh:992
Definition: system.hh:72
Bitfield< 4, 0 > mode
TLB::Translation * translation
ThreadContext is the external interface to all thread state for anything outside of the CPU...
WalkerState funcState
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
STL vector class.
Definition: stl.hh:37
void setTLB(TLB *_tlb)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObject declaration and implementation.
STL list class.
Definition: stl.hh:51
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
uint16_t MasterID
Definition: request.hh:84
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:249
const Params * params() const
Bitfield< 15 > system
Definition: misc.hh:997
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet.
Definition: packet.hh:397
Mode
Definition: tlb.hh:57
virtual const std::string name() const
Definition: sim_object.hh:128
std::vector< PacketPtr > writes
Declaration of the Packet class.
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:102
std::list< WalkerState * > currStates
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:235
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
std::shared_ptr< FaultBase > Fault
Definition: types.hh:238
Bitfield< 3 > addr
Definition: types.hh:79

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