| _decoderFlavor | ArmISA::ISA | protected |
| _params | SimObject | protected |
| _vecRegRenameMode | ArmISA::ISA | protected |
| addStat(Stats::Info *info) | Stats::Group | |
| addStatGroup(const char *name, Group *block) | Stats::Group | |
| afterStartup | ArmISA::ISA | protected |
| assert32(ThreadContext *tc) | ArmISA::ISA | inlineprivate |
| assert64(ThreadContext *tc) | ArmISA::ISA | inlineprivate |
| clear(ThreadContext *tc) | ArmISA::ISA | |
| clear() | ArmISA::ISA | protected |
| clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) | ArmISA::ISA | protected |
| clear64(const ArmISAParams *p) | ArmISA::ISA | protected |
| currentSection() | Serializable | static |
| decoderFlavor() const | ArmISA::ISA | inline |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| dummyDevice | ArmISA::ISA | protected |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| find(const char *name) | SimObject | static |
| flattenCCIndex(int reg) const | ArmISA::ISA | inline |
| flattenFloatIndex(int reg) const | ArmISA::ISA | inline |
| flattenIntIndex(int reg) const | ArmISA::ISA | inline |
| flattenMiscIndex(int reg) const | ArmISA::ISA | inline |
| flattenRegId(const RegId ®Id) const | ArmISA::ISA | inline |
| flattenVecElemIndex(int reg) const | ArmISA::ISA | inline |
| flattenVecIndex(int reg) const | ArmISA::ISA | inline |
| flattenVecPredIndex(int reg) const | ArmISA::ISA | inline |
| getCurSveVecLenInBits(ThreadContext *tc) const | ArmISA::ISA | |
| getCurSveVecLenInBitsAtReset() const | ArmISA::ISA | inline |
| getGenericTimer(ThreadContext *tc) | ArmISA::ISA | protected |
| getGICv3CPUInterface(ThreadContext *tc) | ArmISA::ISA | protected |
| getMiscIndices(int misc_reg) const | ArmISA::ISA | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | SimObject | virtual |
| getProbeManager() | SimObject | |
| getStatGroups() const | Stats::Group | |
| getStats() const | Stats::Group | |
| gicv3CpuInterface | ArmISA::ISA | protected |
| Group()=delete | Stats::Group | |
| Group(const Group &)=delete | Stats::Group | |
| Group(Group *parent, const char *name=nullptr) | Stats::Group | |
| haveCrypto | ArmISA::ISA | protected |
| haveGICv3CpuIfc() const | ArmISA::ISA | inline |
| haveLargeAsid64 | ArmISA::ISA | protected |
| haveLPAE | ArmISA::ISA | protected |
| haveLSE | ArmISA::ISA | protected |
| havePAN | ArmISA::ISA | protected |
| haveSecurity | ArmISA::ISA | protected |
| haveSVE | ArmISA::ISA | protected |
| haveVirtualization | ArmISA::ISA | protected |
| highestELIs64 | ArmISA::ISA | protected |
| impdefAsNop | ArmISA::ISA | protected |
| init() | SimObject | virtual |
| initializeMiscRegMetadata() | ArmISA::ISA | protected |
| initID32(const ArmISAParams *p) | ArmISA::ISA | protected |
| initID64(const ArmISAParams *p) | ArmISA::ISA | protected |
| InitReg(uint32_t reg) | ArmISA::ISA | inlineprotected |
| initState() | SimObject | virtual |
| intRegMap | ArmISA::ISA | protected |
| ISA(Params *p) | ArmISA::ISA | |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| lookUpMiscReg | ArmISA::ISA | protectedstatic |
| memInvalidate() | SimObject | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| miscRegs | ArmISA::ISA | protected |
| name() const | SimObject | inlinevirtual |
| notifyFork() | Drainable | inlinevirtual |
| operator=(const Group &)=delete | Stats::Group | |
| Params typedef | ArmISA::ISA | |
| params() const | ArmISA::ISA | |
| physAddrRange | ArmISA::ISA | protected |
| pmu | ArmISA::ISA | protected |
| preDumpStats() | Stats::Group | virtual |
| readMiscReg(int misc_reg, ThreadContext *tc) | ArmISA::ISA | |
| readMiscRegNoEffect(int misc_reg) const | ArmISA::ISA | |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | Stats::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetStats() | Stats::Group | virtual |
| resolveStat(std::string name) const | Stats::Group | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ArmISA::ISA | inlinevirtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) | ArmISA::ISA | |
| setMiscRegNoEffect(int misc_reg, RegVal val) | ArmISA::ISA | |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| snsBankedIndex64(MiscRegIndex reg, bool ns) const | ArmISA::ISA | inline |
| startup(ThreadContext *tc) | ArmISA::ISA | |
| BaseISA::startup() | SimObject | virtual |
| sveVL | ArmISA::ISA | protected |
| system | ArmISA::ISA | protected |
| takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override | ArmISA::ISA | virtual |
| timer | ArmISA::ISA | protected |
| unserialize(CheckpointIn &cp) override | ArmISA::ISA | inlinevirtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateRegMap(CPSR cpsr) | ArmISA::ISA | inlineprotected |
| vecRegRenameMode() const | ArmISA::ISA | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | EventManager | inline |
| zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) | ArmISA::ISA | static |
| ~Drainable() | Drainable | protectedvirtual |
| ~Group() | Stats::Group | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
