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gem5
v20.0.0.3
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gem5
v20.0.0.3
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These methods relate to the SimObject interface. More...
Functions | |
| virtual const std::string | SimObject::name () const |
| virtual void | SimObject::init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
| virtual void | SimObject::regProbePoints () |
| Register probe points for this object. More... | |
| virtual void | SimObject::regProbeListeners () |
| Register probe listeners for this object. More... | |
| ProbeManager * | SimObject::getProbeManager () |
| Get the probe manager for this object. More... | |
| virtual Port & | SimObject::getPort (const std::string &if_name, PortID idx=InvalidPortID) |
| Get a port with a given name and index. More... | |
| virtual void | SimObject::startup () |
| startup() is the final initialization call before simulation. More... | |
| virtual void | SimObject::memWriteback () |
| Write back dirty buffers to memory using functional writes. More... | |
| virtual void | SimObject::memInvalidate () |
| Invalidate the contents of memory buffers. More... | |
| static SimObject * | SimObject::find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. More... | |
Variables | |
| const SimObjectParams * | SimObject::_params |
| Cached copy of the object parameters. More... | |
| const Params * | SimObject::params () const |
| SimObject::SimObject (const Params *_params) | |
These methods relate to the SimObject interface.
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static |
Find the SimObject with the given name and return a pointer to it.
Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.
Definition at line 171 of file sim_object.cc.
References ArmISA::i, SimObject::name(), and SimObject::simObjectList.
Referenced by Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), DVFSHandler::findDomain(), X86KvmCPU::getMsrIntersection(), and SimObject::unserialize().
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virtual |
Get a port with a given name and index.
This is used at binding time and returns a reference to a protocol-agnostic port.
| if_name | Port name |
| idx | Index in the case of a VectorPort |
Reimplemented in DRAMCtrl, BaseCache, ArmISA::TableWalker, ComputeUnit, IGbE, LdsState, BaseXBar, NSGigE, SimpleCache, Bridge, SerialLink, X86ISA::GpuTLB, SimpleMemobj, BaseTrafficGen, Sinic::Device, X86ISA::Interrupts, DistEtherLink, TLBCoalescer, DmaDevice, BaseCPU, CopyEngine, DRAMSim2, SMMUv3, SimpleMemory, X86ISA::Walker, RiscvISA::Walker, EtherLink, RubyPort, PioDevice, QoS::MemSinkCtrl, AbstractController, GpuDispatcher, MessageBuffer, Network, X86ISA::I8042, ExternalSlave, FastModel::GIC, ExternalMaster, SMMUv3SlaveInterface, System, FastModel::CortexA76Cluster, X86ISA::I82094AA, EtherTapBase, Gicv3Its, RubyTester, X86ISA::I8259, FastModel::CortexA76, X86ISA::Cmos, CommMonitor, MemTest, EtherBus, X86ISA::I8254, RubyDirectedTester, MemDelay, MemCheckerMonitor, GarnetSyntheticTraffic, AddrMapper, and EtherSwitch.
Definition at line 123 of file sim_object.cc.
References fatal, and SimObject::name().
Referenced by CxxConfigManager::bindPort(), EtherSwitch::getPort(), AddrMapper::getPort(), GarnetSyntheticTraffic::getPort(), MemCheckerMonitor::getPort(), RubyDirectedTester::getPort(), MemDelay::getPort(), MemTest::getPort(), CommMonitor::getPort(), RubyTester::getPort(), EtherTapBase::getPort(), FastModel::CortexA76Cluster::getPort(), SMMUv3SlaveInterface::getPort(), ExternalMaster::getPort(), ExternalSlave::getPort(), QoS::MemSinkCtrl::getPort(), PioDevice::getPort(), RubyPort::getPort(), EtherLink::getPort(), RiscvISA::Walker::getPort(), X86ISA::Walker::getPort(), SimpleMemory::getPort(), SMMUv3::getPort(), DRAMSim2::getPort(), BaseCPU::getPort(), DistEtherLink::getPort(), X86ISA::Interrupts::getPort(), BaseTrafficGen::getPort(), SimpleMemobj::getPort(), SerialLink::getPort(), SimpleCache::getPort(), Bridge::getPort(), BaseXBar::getPort(), ArmISA::TableWalker::getPort(), BaseCache::getPort(), DRAMCtrl::getPort(), and SimObject::name().
| ProbeManager * SimObject::getProbeManager | ( | ) |
Get the probe manager for this object.
Definition at line 117 of file sim_object.cc.
References SimObject::probeManager.
Referenced by Prefetcher::Base::addEventProbe(), Prefetcher::PIF::addEventProbeRetiredInsts(), SimObject::name(), BPredUnit::pmuProbePoint(), BaseCPU::pmuProbePoint(), Prefetcher::Base::regProbeListeners(), CommMonitor::regProbePoints(), PowerModel::regProbePoints(), FullO3CPU< O3CPUImpl >::regProbePoints(), AtomicSimpleCPU::regProbePoints(), BaseCPU::regProbePoints(), ArmISA::TLB::regProbePoints(), BaseCache::regProbePoints(), and ThermalDomain::setSubSystem().
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virtual |
init() is called after all C++ SimObjects have been created and all ports are connected.
Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.
Reimplemented in DRAMCtrl, BaseCache, MultiperspectivePerceptron, ArmISA::TableWalker, IGbE, CoherentXBar, Wavefront, Bridge, SerialLink, BaseCPU, ComputeUnit, QoS::MemCtrl, StatisticalCorrector, LoopPredictor, BaseTrafficGen, DistEtherLink, MultiperspectivePerceptronTAGE, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, ArmISA::TLB, X86ISA::Interrupts, DmaDevice, DRAMSim2, SimpleMemory, CpuLocalTimer, SMMUv3, Shader, RubyPort, TraceCPU, QoS::MemSinkCtrl, PioDevice, ExternalSlave, EnergyCtrl, ExternalMaster, MinorCPU, TrafficGen, Iris::BaseCPU, Gicv3, RubyTester, System, X86ISA::I82094AA, CheckerCPU, BaseSimpleCPU, FVPBasePwrCtrl, Network, BaseKvmCPU, AbstractController, SimPoint, CommMonitor, RubyDirectedTester, GarnetExtLink, Process, RubyPortProxy, MemCheckerMonitor, LTAGE, BaseGic, MemDelay, QoS::Policy, AddrMapper, Router, Switch, TAGEBase, QoS::FixedPriorityPolicy, DirectoryMemory, WireBuffer, DMASequencer, GarnetSyntheticTraffic, CacheMemory, Pc, AtomicSimpleCPU, NetworkInterface, TimingSimpleCPU, NoMaliGpu, GarnetNetwork, BasicLink, EtherDump, sc_gem5::Kernel, GarnetIntLink, SimpleNetwork, X86ISA::I8259, and BasicRouter.
Definition at line 73 of file sim_object.cc.
Referenced by RenameMode< ArmISA::ISA >::equalsInit(), LTAGE::init(), SimpleMemory::init(), DRAMSim2::init(), BaseTrafficGen::init(), QoS::MemCtrl::init(), CoherentXBar::init(), CxxConfigManager::instantiate(), and SimObject::name().
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inlinevirtual |
Invalidate the contents of memory buffers.
When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.
This does not cause any dirty state to be written back to memory.
Reimplemented in BaseCache, and BaseTLB.
Definition at line 241 of file sim_object.hh.
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inlinevirtual |
Write back dirty buffers to memory using functional writes.
After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.
Reimplemented in BaseCache, MinorCPU, and RubySystem.
Definition at line 226 of file sim_object.hh.
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inlinevirtual |
Reimplemented in ElasticTrace, and SimpleTrace.
Definition at line 129 of file sim_object.hh.
References SimObject::getPort(), SimObject::getProbeManager(), SimObject::init(), SimObject::initState(), InvalidPortID, SimObject::loadState(), SimObject::params(), SimObject::regProbeListeners(), SimObject::regProbePoints(), and SimObject::startup().
Referenced by System::_getMasterId(), Terminal::accept(), VncServer::accept(), Cache::access(), BaseCache::access(), Prefetcher::AccessMapPatternMatching::AccessMapPatternMatching(), ArmISA::PMU::addEventProbe(), PowerDomain::addFollower(), AtomicSimpleCPU::AtomicSimpleCPU(), SMMUv3SlaveInterface::atsSlaveRecvAtomic(), SMMUv3SlaveInterface::atsSlaveRecvTimingReq(), BaseCache::BaseCache(), BaseCPU::BaseCPU(), BaseTrafficGen::BaseTrafficGen(), CxxConfigManager::bindMasterPort(), CxxConfigManager::bindPort(), Prefetcher::BOP::BOP(), ArmSemihosting::SemiCall::buildDumper(), NetworkInterface::calculateVC(), TraceCPU::checkAndSchedExitEvent(), DVFSHandler::clkPeriodAtPerfLevel(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), CoherentXBar::CoherentXBar(), CommMonitor::CommMonitor(), MemTest::completeRequest(), GenericTimer::CoreTimers::CoreTimers(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), X86ISA::StackTrace::decodePrologue(), Sinic::Device::Device(), Linux::devRandom(), DistEtherLink::DistEtherLink(), Pl111::dmaDone(), DRAMCtrl::DRAMCtrl(), DRAMSim2::DRAMSim2(), FUPool::dump(), SimpleThread::dumpFuncProfile(), ArmKvmCPU::dumpKvmStateCoProc(), DVFSHandler::DVFSHandler(), IdeController::EndBitUnion(), EnergyCtrl::EnergyCtrl(), MessageBuffer::enqueue(), EtherLink::EtherLink(), EtherSwitch::EtherSwitch(), SimObject::find(), FlashDevice::FlashDevice(), FullO3CPU< O3CPUImpl >::FullO3CPU(), BaseCache::functionalAccess(), GarnetSyntheticTraffic::GarnetSyntheticTraffic(), GenericTimerFrame::GenericTimerFrame(), GicV2::getCpuTarget(), FastModel::GIC::getPort(), SimObject::getPort(), ComputeUnit::getPort(), Gicv3Its::Gicv3Its(), GoodbyeObject::GoodbyeObject(), GpuDispatcher::GpuDispatcher(), X86ISA::GpuTLB::GpuTLB(), BaseCache::handleFill(), SimpleCache::handleRequest(), Cache::handleSnoop(), HDLcd::HDLcd(), HelloObject::HelloObject(), CPA::hwWe(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8259::I8259(), IdeDisk::IdeDisk(), IGbE::IGbE(), FetchStage::init(), LocalMemPipeline::init(), ScheduleStage::init(), GlobalMemPipeline::init(), ScoreboardCheckStage::init(), ExecStage::init(), System::init(), ExternalMaster::init(), ExternalSlave::init(), PioDevice::init(), TraceCPU::init(), CpuLocalTimer::init(), DRAMSim2::init(), DmaDevice::init(), BaseTrafficGen::init(), CoherentXBar::init(), BaseCache::init(), DRAMCtrl::init(), Process::initState(), AbstractMemory::initState(), X86ISA::Interrupts::Interrupts(), System::leafMasterName(), Terminal::listen(), VncServer::listen(), SimObject::loadState(), System::lookupMasterId(), MemTest::MemTest(), MemTraceProbe::MemTraceProbe(), SMMUDeviceRetryEvent::name(), SimpleTrace::name(), CopyEngine::CopyEngineChannel::name(), ElasticTrace::name(), PciHost::DeviceInterface::name(), BaseRemoteGDB::name(), RiscvISA::Walker::WalkerState::name(), X86ISA::Walker::WalkerState::name(), ItsProcess::name(), DRAMCtrl::Rank::name(), ArmISA::TableWalker::WalkerState::name(), NoncoherentXBar::NoncoherentXBar(), BaseTrafficGen::noProgress(), MemTest::noRequest(), MemTest::noResponse(), NSGigE::NSGigE(), Linux::openSpecialFile(), TrafficGen::parseConfig(), VoltageDomain::perfLevel(), SrcClockDomain::perfLevel(), Minor::Pipeline::Pipeline(), Pl011::Pl011(), PL031::PL031(), Pl111::Pl111(), PowerDomain::PowerDomain(), BasicRouter::print(), SimpleExtLink::print(), GarnetIntLink::print(), BasicLink::print(), SimpleIntLink::print(), GarnetExtLink::print(), RubyPrefetcher::print(), CacheMemory::print(), MessageBuffer::print(), System::printSystems(), EndQuiesceEvent::process(), AnnotateDumpCallback::process(), CPUProgressEvent::process(), BrigObject::processDirectives(), TLBCoalescer::processProbeTLBEvent(), PowerDomain::pwrStateChangeCallback(), HDLcd::pxlFrameDone(), ThreadContext::quiesceTick(), AmbaFake::read(), IsaFake::read(), UFSHostDevice::readCallback(), PciDevice::readConfig(), UFSHostDevice::readDevice(), IdeDisk::readDisk(), CacheMemory::recordCacheContents(), SMMUv3SlaveInterface::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), NoncoherentXBar::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkSlavePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeSlavePort::recvFunctional(), QoS::MemSinkCtrl::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), SMMUv3SlaveInterface::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), BaseCache::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), HWScheduler::registerNewQueue(), StackDistProbe::regStats(), SimpleNetwork::regStats(), EtherDevice::regStats(), MemFootprintProbe::regStats(), TAGEBase::regStats(), BPredUnit::regStats(), Switch::regStats(), MemTest::regStats(), RubySystem::regStats(), MultiCompressor::regStats(), BaseKvmCPU::regStats(), PowerModelState::regStats(), ThermalDomain::regStats(), HDLcd::regStats(), BaseDictionaryCompressor::regStats(), RiscvISA::TLB::regStats(), AbstractController::regStats(), GarnetNetwork::regStats(), MipsISA::TLB::regStats(), GPUCoalescer::regStats(), Process::regStats(), Router::regStats(), RubyPrefetcher::regStats(), CacheMemory::regStats(), BaseSimpleCPU::regStats(), MinorCPU::regStats(), PowerModel::regStats(), MessageBuffer::regStats(), TLBCoalescer::regStats(), FlashDevice::regStats(), X86ISA::TLB::regStats(), FALRU::regStats(), SMMUv3::regStats(), PowerISA::TLB::regStats(), FullO3CPU< O3CPUImpl >::regStats(), Prefetcher::Queued::regStats(), SnoopFilter::regStats(), X86ISA::GpuTLB::regStats(), QoS::MemSinkCtrl::regStats(), LoopPredictor::regStats(), StatisticalCorrector::regStats(), IdeDisk::regStats(), Sinic::Device::regStats(), BaseCPU::regStats(), SimpleCache::regStats(), Wavefront::regStats(), Prefetcher::Base::regStats(), ComputeUnit::regStats(), ArmISA::TLB::regStats(), System::regStats(), TraceCPU::ElasticDataGen::regStats(), UFSHostDevice::regStats(), TraceCPU::regStats(), UFSHostDevice::requestHandler(), TrafficGen::resolveFile(), Root::Root(), RubyDirectedTester::RubyDirectedTester(), RubyPort::RubyPort(), RubyTester::RubyTester(), VoltageDomain::sanitiseVoltages(), RubySystem::serialize(), CowDiskImage::serialize(), BaseTrafficGen::serialize(), SimObject::serializeAll(), Cache::serviceMSHRTargets(), PowerState::set(), PowerState::setControlledDomain(), WireBuffer::setDescription(), PowerDomain::setFollowerPowerStates(), ConditionRegisterState::setParent(), VecRegisterState::setParent(), LdsState::setParent(), ArmISA::TLB::setTestInterface(), SimpleCache::SimpleCache(), SimpleMemory::SimpleMemory(), SMMUv3::SMMUv3(), Sp805::Sp805(), SrcClockDomain::SrcClockDomain(), MemTraceProbe::startup(), PowerDomain::startup(), BaseKvmCPU::startup(), VoltageDomain::startup(), ArmISA::FsLinux::startup(), System::stripSystemName(), HSADevice::submitDispatchPkt(), HSADevice::submitVendorPkt(), FastModel::GIC::supportsVersion(), SystemCounter::SystemCounter(), ArmISA::TableWalker::TableWalker(), ThermalModel::ThermalModel(), GarnetSyntheticTraffic::tick(), MemTest::tick(), TimingSimpleCPU::TimingCPUPort::TimingCPUPort(), TimingSimpleCPU::TimingSimpleCPU(), TLBCoalescer::TLBCoalescer(), TraceCPU::TraceCPU(), Prefetcher::Queued::translationComplete(), DrainManager::tryDrain(), RubyPort::trySendRetries(), UFSHostDevice::UFSHostDevice(), ArmSemihosting::unrecognizedCall(), Sinic::Base::unserialize(), SimObject::unserialize(), BaseTrafficGen::unserialize(), NSGigE::unserialize(), BaseTrafficGen::update(), DerivedClockDomain::updateClockPeriod(), TraceCPU::updateNumOps(), VncInput::VncInput(), VoltageDomain::voltage(), DVFSHandler::voltageAtPerfLevel(), VoltageDomain::VoltageDomain(), AmbaFake::write(), IsaFake::write(), PciDevice::writeConfig(), UFSHostDevice::writeDevice(), IdeDisk::writeDisk(), SimObjectResolver::~SimObjectResolver(), and SMMUv3::~SMMUv3().
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Definition at line 119 of file sim_object.hh.
References SimObject::_params, SimObject::SimObject(), and SimObject::~SimObject().
Referenced by VirtIO9PSocket::connectSocket(), ElasticTrace::ElasticTrace(), MultiperspectivePerceptron::SGHISTPATH::getHash(), GoodbyeObject::GoodbyeObject(), HelloObject::HelloObject(), MultiperspectivePerceptron::init(), SimObject::name(), RawDiskImage::notifyFork(), CowDiskImage::notifyFork(), BaseMemProbe::regProbeListeners(), StackDistProbe::regStats(), PowerModelState::regStats(), ThermalDomain::regStats(), PowerModel::regStats(), ArmISA::PMU::setThreadContext(), VirtIO9PDiod::startDiod(), and TAGE::TageBranchInfo::~TageBranchInfo().
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Register probe listeners for this object.
No probe listeners by default, so do nothing in base.
Reimplemented in Prefetcher::Base, ArmISA::PMU, ElasticTrace, SimPoint, BaseMemProbe, and SimpleTrace.
Definition at line 112 of file sim_object.cc.
Referenced by CxxConfigManager::instantiate(), and SimObject::name().
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Register probe points for this object.
No probe points by default, so do nothing in base.
Reimplemented in BaseCache, ArmISA::TLB, BaseCPU, AtomicSimpleCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, PowerModel, CommMonitor, and BPredUnit.
Definition at line 104 of file sim_object.cc.
Referenced by CxxConfigManager::instantiate(), SimObject::name(), and PowerModel::regStats().
| SimObject::SimObject | ( | const Params * | _params | ) |
Definition at line 55 of file sim_object.cc.
References SimObject::probeManager, and SimObject::simObjectList.
Referenced by Workload::fixFuncEventAddr(), and SimObject::params().
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startup() is the final initialization call before simulation.
All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.
Reimplemented in DRAMCtrl, VirtIO9PSocket, BaseCPU, VirtIO9PDiod, SrcClockDomain, DistEtherLink, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, RealViewOsc, DRAMSim2, Prefetcher::AccessMapPatternMatching, MuxingKvmGic, ThermalModel, BaseSimpleCPU, MaltaIO, EnergyCtrl, MinorCPU, X86ISA::I8254, ArmISA::FsLinux, VoltageDomain, Root, System, X86ISA::Cmos, RubySystem, ArmV8KvmCPU, MathExprPowerModel, BaseKvmCPU, CommMonitor, HelloObject, PowerDomain, ArmKvmCPU, MemTraceProbe, BaseArmKvmCPU, sc_gem5::Kernel, and X86KvmCPU.
Definition at line 96 of file sim_object.cc.
Referenced by ThermalModel::addNode(), SrcClockDomain::clkPeriodAtPerfLevel(), X86ISA::ISA::flattenMiscIndex(), SimObject::name(), RiscvISA::ISA::startup(), System::startup(), ArmISA::FsLinux::startup(), MipsISA::ISA::startup(), PowerISA::ISA::startup(), SparcISA::ISA::startup(), MuxingKvmGic::startup(), CxxConfigManager::startup(), ArmISA::ISA::unserialize(), ArmISA::ISA::vecRegRenameMode(), and RealViewOsc::~RealViewOsc().
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protected |
Cached copy of the object parameters.
Definition at line 111 of file sim_object.hh.
Referenced by GenericTimer::createTimers(), ArmPPIGen::get(), BasicRouter::params(), SimpleExtLink::params(), X86ISA::I8237::params(), BasicLink::params(), BaseInterrupts::params(), PowerISA::Interrupts::params(), MipsISA::Interrupts::params(), EtherDevice::params(), MmDisk::params(), BadDevice::params(), EtherSwitch::params(), DumbTOD::params(), MemCheckerMonitor::params(), FaultModel::params(), Uart::params(), AmbaFake::params(), IsaFake::params(), X86ISA::Speaker::params(), QoS::PropFairPolicy::params(), EtherBus::params(), EtherTapBase::params(), RiscvISA::Interrupts::params(), X86ISA::ISA::params(), SimpleIntLink::params(), CommMonitor::params(), PowerState::params(), RealView::params(), BaseGic::params(), BasicExtLink::params(), SparcISA::Interrupts::params(), ArmISA::Interrupts::params(), Sinic::Base::params(), Network::params(), X86ISA::I8254::params(), MaltaCChip::params(), Uart8250::params(), BasicIntLink::params(), X86ISA::I8259::params(), X86ISA::I82094AA::params(), Root::params(), PL031::params(), Trace::ArmNativeTrace::params(), MaltaIO::params(), RiscvISA::ISA::params(), Gicv3::params(), SimObject::params(), X86ISA::I8042::params(), Iob::params(), SMMUv3SlaveInterface::params(), EtherDevBase::params(), Sp804::params(), MipsISA::ISA::params(), IdeController::params(), EtherTapStub::params(), PowerISA::ISA::params(), EtherLink::params(), A9GlobalTimer::params(), RealViewCtrl::params(), CpuLocalTimer::params(), CopyEngine::params(), VGic::params(), RiscvISA::Walker::params(), X86ISA::Walker::params(), X86ISA::Interrupts::params(), DistEtherLink::params(), SparcISA::ISA::params(), GenericTimer::params(), Pl111::params(), GicV2::params(), IGbE::params(), ArmISA::ISA::params(), ArmISA::TableWalker::params(), and CheckerCPU::setSystem().
